Design And Implementation Of High Speed Data Transmission System Based On FPGA

With the continuous development of Internet communication technology,System on Chip have been more and more widely used in the fields of big data transmission and real-time communication.The traditional Ethernet transmission method based on single-chip microcomputer as the core processor or using TCP protocol is limited by the CPU data processing capacity and transmission bandwidth,as well as the complex flow control mechanism and congestion control mechanism of TCP protocol,so the system often fails to reach the needs of high-speed data transmission.For the case,this thesis aims at designing and developing an FPGA-based high-speed data transmission system,and using the UDP protocol to realize the data transmission among communication devices to achieve the purpose of high-speed data transmission.The system is mainly divided into two large modules for design,respectively,the design of the UDP/IP protocol stack and the design of the MAC controller.The ARM controller is responsible for the control of the FPGA data operation of the whole system,combined with the flexible configuration characteristics of the FPGA to make the whole system more flexible for data transmission.The UDP/IP protocol stack is mainly responsible for encapsulating and splitting data,adding or removing IP and UDP data headers,and the MAC controller is mainly responsible for sending and receiving MAC frames,and a parallel CRC check module is designed to detect errors in MAC frames.In addition,rule filtering of data is implemented in the MAC controller,and packets that do not meet the rules are discarded by setting a 5-tuple,which improves the adaptability of the system in the face of complex network conditions.For the problem of insufficient storage space inside the FPGA,the combination of FPGA+DDR is designed.The DDR storage system outside the protocol stack is responsible for caching a large amount of data in burst,which enhances the processing capability of the whole system in the face of large data.When the modules in the system communicate data through FIFO,ping-pong operation is used for optimization,which reduces the waiting time of data in FIFO and realizes seamless data connection.Finally,the whole system can realize data transmission over different sizes of Ethernet by combining with different IP cores and the use of configurable FIFOs.The whole system is designed based on the Zynq7000 MZ7035 FA development board and Vivado integrated design environment is used as the development tools for writing logical code.The experiments has verified that all functions of the system work properly.A comparison has been made between data transmission on the CUP and on the FPGA under the same conditions,and it can be found that the data transmission on the FPGA has a significant speed increase and can play an intercepting role for packets that do not meet the expected rules.The data transmission reaches 112 MB/s on FPAG over Gigabit Ethernet network and 855 MB/s on FPGA on 10 Gigabit Ethernet network,and it is able to complete the rate conversion between Gigabit Ethernet and 10 Gigabit Ethernet.Finally,the function of the whole system meets the preliminary design standard.