High-speed And Large-capacity Radar Signal Transmission And Storage Based On Multi-channel Parallel Optical Modules

The phased array radar scans the detection area by controlling the phase of the current fed to each radiating unit and continuously changing the beam direction.It often has the characteristics of multiple tracking targets,short response time,and high data rate.This requires the radar system to have high-speed data transmission and large-capacity data storage capabilities.At the same time,for the needs of the battlefield environment,the radar signal processing system may not be integrated with the antenna array,but the signal sampling board will transmit DBF data to the rear signal processing system.According to the phased array radar system's requirements for echo data transmission and storage,a multi-channel parallel optical module is proposed as the interface between the signal sampling board and the signal processing system.The system uses a signal transmission and storage board as the bridge between the signal sampling board and the signal processor,and 12 parallel optical modules on the board receive the radar echo data transmitted by the signal sampling board to achieve data transmission at a distance of 100 meters.The data is temporarily stored in the signal transmission and processing board cache module,and transmitted to the upper computer disk array through the PCIE 3.0interface under the control command of the upper computer program.In order to achieve highspeed data transmission and large-capacity data storage,this paper completes the overall system design of the system,and complete the hardware design of the signal processing board with Xilinx Virtex-7 FPGA chip as the core processor.The following modules work:(1)Optical module data transmission.In this paper,FPGA,optical transmit/receive module,and optical fiber are used to form a transmission loop.At the same time,a signal generation and 12-channel data distribution module is designed.The Gigabit transceiver interface is used to interconnect the electrical interface with the optical module,and the data transmitted through the optical module link is provided to the DDR3 cache module through bitwidth conversion.(2)DDR3 data cache.This article uses Xilinx MIG IP core to achieve read and write timing control of DDR3 chip.In order to solve the problem that the DDR3 module read data operation and write data operation cannot be performed at the same time,this article designed a DDR3 cache with a ping-pong structure.To achieve pipeline operation,the command to control DDR3 read and write data is issued by the host computer.In order to match the host computer interface,the data and command interface of the DDR3 module is packaged into an AXI-4 interface.(3)PCIE 3.0 bus transmission and host computer disk array storage.This part first analyzes the PCIE 3.0 bus topology and hierarchical structure,and completes the base address register configuration and transaction grouping.The system adopts DMA to realize the process that the host computer sends control commands to the board and the board DDR3 module transmits data to the host computer through the PCIE 3.0 bus.The data transmitted to the host computer is stored in the host's disk array.After the loopback test of the optical module part transmission and the verification of the data stored in the host computer,the system works well when the line rate of the 12-channel parallel optical module is 6.25Gbps;the data width of the DDR3 cache module is 64 bits,and the whole memory capacity is 4GB;the capacity of the host computer is 1.5TB,which can meet the actual radar requirements.The project implemented in this paper,as a general high-speed large-capacity data transmission and storage system,can be applied to the signal processing field including radar systems.