Research And Design Of Codec Based On HDMI Protocol

Generally,the video receiving and sending in the design of video display system are completed by independent and special video transceiver chip.Generally speaking,video transceiver chip has a large volume,needs to occupy a certain size of PCB area,and video transceiver chip needs a lot of I/O ports for connection;in multi-channel video display system,this disadvantage is particularly prominent.In this paper,FPGA based HDMI encoder and decoder are designed to solve the above problems based on the research of HDMI protocol.It conforms to HDMI version 2.0 standard,and is compatible with HDMI version 1.4b and lower standards.It has the ability to encode and decode video data and packets.In this paper,its simplified and only keeps the necessary functional modules;HDMI encoder is mainly composed of ECC circuit,transmission control module,multiplexer,scrambler and HDMI data type encoder,HDMI decoder is mainly composed of ECC circuit,demultiplexer,descrambler,HDMI data type decoder,character alignment and channel binding module.The bandwidth of the codec is improved by parallel design of each functional module,and based on this way,two character and four character parallel HDMI codec are designed respectively.HDMI codec logic circuit is realized through FPGA reconfigurable logic resources,and serial and parallel signals are converted through FPGA integrated high-speed serial transceiver.For HDMI codec based on FPGA,the extra PCB area is not needed,and the inter chip I/O port is not needed;the design flexibility is improved,and the design cost is reduced.The test results show that each functional module meets the expected requirements,HDMI codec meets the HDMI version 2.0 standard,and can accurately encode and decode.The parallel HDMI codec can encode and decode 4K@60Hz video at most.The image scaling module based on bilinear interpolation algorithm is designed to solve the problem that the video format of the source meets the needs of the receiver.It mainly includes input buffer,output buffer,row and column interpolation calculation and interpolation control circuit.Its designed based on FPGA in this paper,and it is tested by functional simulation.The test results show that the module meets the expected scaling requirements and can scale up to 1080p images.