Design And Realization Of HDMI Receiver PHY

Here we base on SMIC 0.13μm CMOS Logic process, analysis and design the HDMI Receiver PHY to compliance with HDMI specification version 1.3. The target of this design is to achieve the data rate of 4.95Gpbs. This design integrates the differential signal receiver, data sampling module and de-serializer module, CDR(DRL) and decoder module.This thesis provides the structure of HDMI Receiver PHY, describes the HDMI core encoder/decoder method; And also analysis the key issues inside high-speed receiver circuit such as skew, jitter and sampler metastability. Base on the analysis, several solutions were provided and implemented. Further than that, the HDMI Receiver PHY was taped out and tested. The testing shows an excited that system work normally and can light on LCD without any observable error.