Research On RISCV SoC Layout Design Of Deep Submicron Technology

IC design refers to the complete process from circuit conception to chip production.According to the different responsibilities shared by each step in the process,it is roughly divided into the front-end hardware logic realization and the back-end layout physical realization.The introduction and continuous development of the RISCV instruction set architecture has made hardware logic design different from the previous ideas and perspectives,and the rapid progress of chip manufacturing technology has also caused many new problems to be solved in the physical layout implementation process.The problems of circuit parasitics,electromigration,and noise interference after the manufacturing process enters deep submicron are becoming more and more serious.It is necessary for engineers to develop more advanced EDA tools and develop more scientific layout designs based on the characteristics of integrated circuit process development.Skills can shorten the layout convergence cycle and meet today's market requirements for SoC.The paper completed the back-end layout design of the entire RISCV SoC chip based on Synopsys series advanced SoC design verification platforms Design Compiler and IC Compiler.The paper introduces the RISCV architecture instruction set and the logic realization concept of the front-end circuit of the SoC chip,focusing on the comprehensive design of testability,the realization of low-power strategy,static timing analysis,automatic placement and routing,etc.,and the physical realization process of the chip is proposed.And to improve the quality of the layout,the layout design of a 140,000 gate chip was successfully completed under the deep sub-micron manufacturing process.This chip has exploratory significance for the realization of RISCV architecture SoC chips,and also provides reference value for the layout problems and solutions brought by deep sub-micron technology.This design uses DC's Topography technology during logic synthesis to reduce the impact of delay inaccuracy on chip timing.During the scan design,the test coverage is improved by "bypassing" the memory module and repairing the uncontrollability of the clock.Through multi-threshold voltage optimization,the method of clock gating circuit unit insertion and block access to the memory greatly reduces the power consumption of the SoC chip.Two scenario-corresponding function modes and scanning modes are set for the chip,so that the EDA tool can take into account the optimization of timing,area,and power consumption in the two scenarios,and finally make the chip work normally in each working environment.In the chip layout planning stage,through continuous iterative optimization,the power network design that meets the requirements of voltage drop and electromigration is finally completed[12].The most commonly used binary tree structure is used to complete the design of the functional clock and the test clock,and the various parameters of the clock tree meet the requirements.In the process of static timing analysis,first obtain the parasitic parameters of the whole chip on the StarRC platform,and then import the PrimeTime platform to speed up the timing closure,and have a higher circuit timing analysis coverage than other platforms,and finally complete the timing.Sign for delivery.By adding reverse-biased diodes to the ground,increasing the width of wiring,expanding metal line spacing,inserting filling cells,adding redundant vias,etc.,the manufacturability problems of the chip are avoided.