A Study And Design Of Layout For USB Power Switch Base On0.18μm CMOS Process

Along with the computer’s application, there are more and moreperipherals. Outside of the case appeared a variety of peripheral interfaces. Dueto increasing of external devices, resources of the computer used to connect aperipheral are not enough. Lack of interface, conflicts may happen between allsorts of I/O. Because of lacking a bus that is bidirectional, low-cost, plug andplay, low-speed peripherals limit the external equipment development. In thiscontext, several computer manufacturers in the industry, developed USB businterface which is suitable for the external devices used in low speed. It is atypical bus with equipment inserting the shelf.Design of this article is based on the demand of the market, this paperproposes a research and design of layout for USB power switch based on.18μmCMOS. As a management unit of USB power management system, USB powermanagement system must be able to detect load connection status at any time,and to provide certain power for load. When system is short of power supply orthe system temperature is over the normal operating temperature range, theprotection may happen. And at the same time, the system sends out errorindication signal to notify the USB controller, to keep the USB system normal.This chip of the article includes enable circuit, bias circuit, over-currentprotection, under-voltage protection, over temperature protection, and the basicunit such as logic circuits. Chip manufacturing technology is based on the0.18μm CMOS GSMC, design and simulation of the circuit and layout are on theplatform of Cadence. The article makes a detailed description to the design. First, it presents theoverall design scheme. Then it presents the theoretical analysis of each functionmodule in detail, and gives a design scheme of the module and simulation. Thesemodules include: bias circuit, under voltage protection, over temperatureprotection, oscillator, charge pμmp, over-current protection. Finally, the wholecircuit is simulated. The simulation results meet the design targets. This paperadopts the full custom layout design, Layout design evades the risks of the massproduction as far as possible, including the power cord, anti-interference,matching, interconnection line, ESD protection, antenna effect, the latch upeffect, etc. By thrice optimized of ESD，two tests of ESD test targets，butthrough twice correcting，The difficulty had been solved. Do LVS for layoutand circuit by using CADENCE software package CALIBRE tools, untilcompletely correct. The design is strictly under control on every step. By thricecorrecting, through the test, the chip has function,and attain goal ofmass-produce.