Analysis Of Performance And Study Of Layout Algorithm On The Architecture Of NoC

As the steady growth of chip scale and operating frequency, sharing the bus can't satisfy the demand of the large-scale system obviously. Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The regular tile-based NoC architecture was recently proposed as a solution to the complex on-chip communication problems. Such a chip consists of a grid of regular tiles where each tile can be a general-purpose processor, a DSP, a memory subsystem, etc. A router is embedded within each tile with the objective of connecting it to its neighboring tiles. Thus, instead of routing design-specific global on-chip wires, the inter-tile communication can be achieved by routing packets. The performance and the effciency of the NoC depend on the underlying communication infrastructure. Thus, the design of effcient, high performance communication infrastructure represents a critical issue for the success of the NoC approach.Layout is just optimizal technology on the communication infrastructure, through which Network topology found one advantage architecture that is belong to system level. In this paper, we first introduced current instance about network topology in the world. Then, proposed and designed the spidernet topology. By Comparing with node degree, network diameter, connect degree, average most short path, average most short wire, we found that the spidernet has good properties with the bigger node degree, smaller network diameter and shorter average most short path; in addition, it still has the advantage that can flat on one plane, which make chip low cost, with high performance.In the paper, we focus on low power layout at the system level, which partitions the system description into the wire length and area constraints; through comparing influencing power in the chip, our purpose is that finding best performance after layout with physical architecture. This paper presents three kinds of layout algorithms: the rand-based algorithm, the enumeration algorithm and the rand-and-enumeration algorithm. The rand-based algorithm is choose best layout in as many as possibly irrelevant layout. The enumeration algorithm find out superior layout in all layouts, this algorithm has the good layout result and a stronger optimizion but the higher complexity. Random enumeration chooses the layout under the condition of random initialization.In the paper, the random-based algorithm takes O(n~2) time. Enumeration algorithms takes O(n~2n!) time complexity and the following takes O (n~2log n)time complexity.