Design And FPGA Implementation Of 5G NR Fronthaul

Although 5G has entered the commercial stage,the deployed networks are composed of high-cost macrocell base stations currently,and the high rate and wide coverage of 5G will depend on small base stations in the future.The integrated small base station has been greatly challenged in the fifth era of portable systems.The Cloud Radio Access Network(C-RAN)based on the centralized baseband unit(BBU)and radio remote unit(RRU)will get an increasingly wide utilization.The fronthaul channel is an important part of connecting the BBU and RRU in the C-RAN architecture.This thesis provides a set of practical fronthaul channel solutions for small base stations based on C-RAN.The thesis analyzes signal processing tasks in the physical layer of the uplink and downlink in 5G small base stations,comprehensively considering the main factors such as processing complexity,data flow direction,and the amount of transmission data which define the functions that the fronthaul channel needs to implement;on this basis,the key modules of the fronthaul channel are designed and implemented based on FPGA which is used as a development platform.The specific work of the thesis includes:First,the uplink and downlink data processing flow of the small base station system in the physical layer are comprehensively analyzed,and the baseband algorithms that need to be implemented in the fronthaul FPGA are defined,mainly including the frequency domain to the time domain of the downlink signal,the time domain to the frequency domain of the uplink signal and random access channel preamble reception processing.Second,the 5G random access process is studied.MATLAB is used to build a link-level simulation to simulate the random access preamble receiving algorithm,which provides design support for the implementation of the random access algorithm on the FPGA.Third,the Intel A10 FPGA’s 10 Gigabit Ethernet hard core is used to implement the data transmission interface with the RRU;the PCIE hard core is used to implement the data interface with the CPU,and the matching module is designed and implemented.Fourth,the main functional modules are designed and implemented such as downlink frequency domain to time domain conversion processing,uplink time domain to frequency domain processing,and random access channel signal processing,and are connected to 10 Gigabit Ethernet and PCIE interfaces to form a complete Fronthaul channel.The fronthaul FPGA can support data from three cells and four antennas.The theoretical transmission rate can reach 47Gbps.Simulation results show that the downlink processing delay is 0.014ms and the uplink processing delay is 0.048ms,which meets the design requirements.