The Design And Implementation Of FPGA-based Programmable Precise Network Message Structure And Sending Unit

With the popularity of the network and the massive construction of network infrastructure,the demand for network performance testing is becoming more and more urgent.Therefore,developing a high-precision,high reliability,cost-effective network performance tester has a very important value of engineering applications,can be widely used in many communications networks,communications,electronics and other fields.This paper mainly completes the architecture design of network performance tester system and the design and implementation of programmable accurate network message construction and sending unit based on Field Programmable Gate Array(FPGA).First of all,the paper introduces the network protocol related network performance tester system,and gives the overall framework of the network performance tester system;Second,the system performance requirements of the network performance tester system is given to achieve programmable and accurate network packet structure and sending unit,And complete the design and simulation of each module in the scheme.Then,the construction and sending unit of network message are debugged on the platform of network performance tester system,and the basic functions and performance of network packet construction and sending unit are verified At last,the design scheme of network packet construction and transmission unit based on PCIe interface is given,and the system architecture of network performance tester is improved.Through debugging,the network packet construction and sending unit functionally realizes the accurate construction of various network packets and the control of multiple scheduling modes and sending modes,and achieves the performance of sending at a rate of one gigabit full-frame Festival for the accuracy of units and real-time reporting statistics and other requirements.