Design Of A Digital Decimation Filter In Sigma-Delta ADC

Today's society,integrated circuits(ICs)are everywhere.With the trend of digital integrated circuits becoming mainstream and the rapid development of digital signal processing technology,the conversion interface between analog and digital signals-analog-to-digital converter(ADC)is gaining more and more attention.Sigma-Delta ADC obtains high conversion accuracy through the use of oversampling and noise shaping technology.The application field involves many aspects such as biomedicine,intelligent hardware,audio,industrial control,etc.It is the focus of ADC research.A complete Sigma-Delta ADC structure mainly includes an anti-aliasing filter,a Sigma-Delta modulator and a digital decimation filter as the final stage,where the digital decimation filter is related to the power consumption and area of the overall Sigma-Delta ADC chip.It is especially important to design a digital decimation filter and have the advantages of low area and easy application.This paper presents a Sigma-Delta ADC digital filter,which can filter down the high frequency noise while downsampling the input signal from 32 to 512 times.The digital filter cooperates with the control circuit when working,adjusts the decimation rate by configuring internal registers to change the effective number of output data,the circuit can output 24-bit standard ADC conversion data.The main research contents and results of this article are as follows:1.Summarize the principle and structure of Sigma-Delta ADC,and analyze the processing of signal and noise in the modulator in the frequency domain.A three-stage cascade of integrators feed forward structure modulator model is built in Simulink,using a single quantizer,and the structural parameters of the modulator are determined through simulation.The sampling frequency of the obtained modulator model is 332.8KHz,and the signal-tonoise distortion ratio of the output data is 122.94 d B,the effective number of bits is 20.13 bits,and the noise shaping effect is well.2.Designed and optimized the digital decimation filter in Sigma-Delta ADC.Comprehensively considering various factors such as bandwidth,hardware resources,power consumption,etc.,according to the design index of the digital decimation filter,the digital filter structure is selected as a four-stage cascade integrator comb(CIC)filter,which is implemented by a recursive structure.A filter simulation model was built in Simulink and co-simulated with the modulator model to form a Sigma-Delta ADC system.The signal-tonoise distortion ratio in the output spectrum is up to 120.58 d B with an accuracy of 19.74 bits.It shows that the performance of the digital decimation filter is good.3.The Verilog HDL language is used to design the digital decimation filter and control circuit,including the design and function simulation of circuit modules such as register read and write,reset and clock generation,decimation filter,circuit mode conversion and data output.The spectrum analysis of the digital filter output data shows that the decimation filter works normally and has good performance.Under the GSMC 0.18?m process,use Design Compiler to complete the logic synthesis of the design,report shows no timing violations in design.