The Design Of Sigma-Delta ADC Based On Reconfigurable Decimation Ratio

The progress of science and technology has promoted the development of communication and signal processing towards to the digital trend.As the interface between analog and digital signal,Sigma-Delta ADC plays an important role in digital communication and signal detection due to its high precision,easy integration and low noise.Sigma-Delta ADC consists of modulator and digital downsampling filter,digital decimation filter plays a decisive role on the chip area,and output ports of the filter directly connect to digital processing system,so optimizing the decimation filter and digital interface circuit can help to improve the performance of data acquisition and processing system.This paper aims to design a high-precision Sigma-Delta A/D converter that can be configured at the rate of extraction,and enrich the function of digital interface,and increase the effective number by adjusting the output rate of the data.The modulator uses a fourth-order feedforward structure,a quantizer with a upsampling rate of 128 and a sampling clock frequency of 2048 KHz.Firstly the working principle of the modulator and non-ideal factors influencing the performances of modulator are introduced,then using Matlab/Simulink to model system level of modulator,finally the design of integrator,quantizer and two phase clock circuit that does not overlap are completed on Cadence platform.Digital downsampling filter adopts three-level extraction structure,which consists of CIC filter,compensation filter and half-band filter.The scope of the extraction factors can be configured for 128,256,512,1024,2048,4096,8192,16384.the structure of all subfilters are optimized,sharpening function is used to sharpen the transfer function in CIC filter,which improves the attenuation of the filter and the rolling drop of the band.The half-band filter adopts an novel non-sensitive structure,which reduces the hardware consumption and sensitivity of the frequency response to the coefficient quantization.In addition,the parallel symmetric structure and the CSD code are adopted to further optimize the area in both compensation filter and half-band filter.the behavior level modeling of the filter is conducted based on Matlab.The passband band ripple and the stopband attenuation of the filter is less than 0.01 d B and-100 d B respectly,and the maximum output sampling frequency is 16 k Hz.Then,the RTL level description of the filter is performed by Verilog,and the clock frequency division circuit and SPI interface circuit are designed to complete the logic function simulation.Using Cadence and So C Encounter respectively complete the layout of modulator and decimation filter based on the 0.35 um COMS process,the core area is,after extracting the netlist parameters,post-simulation was carried out,at the same time,the FPGA verification for the function of filter is conducted.The target signal and the sampling frequency are set as 31.25 Hz and 2048 Hz respectly.The simulation results show that the SNR of the circuit is about 104.7d B when the extraction factor is 128,and,the SNR is about 125.5d B when the extraction factor is increased to 13684.