The Design And Optimization Of Digital Decimation Filter For Sigma-Delta ADC

Analog-to-digital converters (ADC) are important building blocks in modernanalog/mixed-signal ICs. In addition to static and dynamic performance, areaconsumption and power dissipation have become important issues in the design of ADCas more signal processing systems are increasingly targeted to be portable andbattery-operated. Sigma-Delta ADC employs oversampling technique to increase itsSignal-to-Noise Ratio and conversion accuracy, which is a preferred choice for manyhigh-resolution applications, such as life detector, seismic detector and gyroscope.Sigma-Delta ADC is composed of two main blocks, Sigma-Delta modulator anddigital decimation filter. The digital decimation filter, consisting ofCascade Integrator Comb filter (CIC) followed by compensator filter and half-bandfilter, consumes larger amounts of area and power comparatively. Substantial power isdissipated in conventional CIC filter as it operates under high sampling rate. Huge areais consumed by conventional compensator filter and half-band filter because largenumber of registers is needed to store their respective coefficients. Therefore, a carefulconsideration of the filter’s structure is essential to design a low-power andarea-optimized Sigma-Delta ADC. The objective of this thesis is to design and build thedigital part of a Sigma-Delta ADC aiming at reducing area and power.In this thesis, an improved digital decimation filter architecture is proposed. Thearchitecture includes a five-stage cascaded CIC filter, a compensator filter and atwo-stage cascaded half-band filter. In order to reduce the area consumption and lowerthe power dissipation, recursive structure is implemented in the CIC filter to lower thesampling rate at the intermediate stage, and CSD number is used in coding the filtercoefficient to cut down the numbers of required registers.The proposed techniques are applied to the design of a18-bit Sigma-Delta ADCusing0.18um CMOS technology, with input sampling frequency of1024kHz andoutput sampling frequency of2kHz. Simulation results show that with a downsamplingratio of512times, an ENOB of18.3bits and an SNR of110dB are achieved. Theentire filter consumes a power of410mW at3.3V supply with an area of 1.3x1.3mm~2.