Design Of A Low Power Digital Decimation Filter For Sigma-Delta ADC

The sigma-delta analog-to-digital converter(ADC)is a low-speed,high-precision oversampling ADC.In recent years,due to its properties of low power consumption,high linearity,and high resolution,sigma-delta ADC has been widely applicated in digital signal processing,digital communication systems,high-fidelity audio and video,precision measurement and other aspects.The composition of sigma-delta ADC has two parts:a sigma-delta modulator and a digital decimation filter.The sigma-delta modulator is primarily responsible for modulating the input signal and then outputting high-speed,low-precision digital signals.The digital decimation filter is mainly responsible for filtering and down-sampling the high-speed and low-precision digital signals to output a high-precision digital signal at a Nyquist rate.In general,the accuracy and conversion speed of a sigma-delta ADC are majorly depended on the modulator,while the area and power consumption are mainly determined by the digital decimation filter.Obviously,high-power consumption and large-area products are no longer adaptable to current trends.The purpose of this thesis is to design a low-power,smali-area digital decimation filter for using in 16-bit sigma-delta ADCs.The digital decimation filter designed is based on practical engineering applications in this thesis.After consideration,the Cascaded Integrated Comb(CIC)filter,Finite-impulse-response Compensator(CFIR)and half-band(HB)filter are selected to cascade to implement the whole digital decimation filter.In the design,the Noble Identical Principle,Recursive Structure,Polyphase Decomposition technique,filter Coefficient Symmetry technique and Canonical Signed Digit(CSD)Coding technique are used to optimizate and improve structures or algorithms of CIC filter,CFIR filter and HB filter,we can simplify the structures,reduce effective coefficients and cut down the computations.On the foundation of above-mentioned,on the one hand,according to patity of filter's length,the 'thesis proposed a kind of Parity Optimization method to optimizate and improve filter's structures;on the other hand,a divide algorithm was proposed to reduce the time consumption for ADC's calibration procedure.Combining these twos methods with some of existing technical methods that mentioned previously,it can reduce the power consumption and area of the digital decimation filter to a great extend.Based on CMOS 110nm process,Register Transfer Level design and back-end implementation have been finished.The post-simulation results show that under the circumstance of 10MHz sampling frequency,5016.326904 kHz sinusoidal input signal frequency and 256 times down-sampling rate,the signal to noise and distortion ratio(SNDR)of the digital decimation filter is 91.1 dB,the effective number of bits(ENOB)is 14.84 bit,and there is no spurious dynamic range(Spurious).Free Dynamic Range(SFDR)is 95.6 dB,and Total Harmonic Distortion(THD)is-95.6 dB.The area of digital circuit(with SPI)is about 0.25 mm2,and the total power consumption is only 376 ?W at a power supply of 1.5 V.Compare to other same type's references,less power consumption and area were implemented in the design.