The Research And Design Of Decimation Filter With Flexible Decimation Rate Used In Sigma-Delta ADC

Sigma-Delta ADC is an oversampling Analog-to-Digital Converter with high resolution and low transition rate. These converters exploit the enhanced speed and circuit density of modern VLSI technologies and overcome limitation on resolution that result from the component mismatching. Now sigma-delta ADC has been widely used in the fields of signal processing, digital communication, automation control and multimedia. So far, sigma-delta ADC with 24 bit resolution has the highest resolution in industry.The resolution and conversion speed of sigma-delta ADC are determined by the performance of the modulator, but its area and power consumption are mainly determined by the decimation filter. The principles and design methods of the decimation filter are studied in this thesis. Furthermore, the ways to optimize the circuit architecture and improve the circuit performance are analyzed. On the other hand, for a given oversampling frequency, decimation filter with fixed orders and fixed coefficients also fixs the bandwidth of input signal and the resolution of output signal, resulting in the limitation on the fields of sigma-delta ADC can be used, which is a waste of design time and resource.In order to solve problems mentioned above, this thesis introduces a decimation filter with flexible decimation rate, which is used in a wireless sensor network chip. The oversampling frequency of the Sigma-Delta ADC is 4 MHz, and the input signal has four different bandwidths: 3 k, 7 k, 15 k, 31 k. For different bandwidth input signal, the orders and the coefficients of the decimation filter can be selected by the external control signal, so the output can also has four different resolutions: 14 bit, 12 bit, 10 bit, 8 bit.The whole design flow consists of Matlab system simulation, RTL coding of the decimation filter, DC synthesis, timing and function verification, placement and routing. The chip has been implemented in Hua Hong NEC 0.25μm COMS process, and the layout is shown at the end of this thesis.