Research And Design Of The Decimation Filter Of Wideband Countinuous Time Sigma-delta ADC

With the rapid development of wireless communication systems,bandwidth,speed and power consumption have become the key requirements of electronic systems.The characteristics of intelligence,integration and miniaturization of electronic information systems are becoming more and more prominent.In recent years,RF front-end integrated chips with RF,analog / mixed signal functions have become an important direction of high-end integrated circuits.High-speed,wide-bandwidth,large dynamic analog signal acquisition and digital signal processing technology has become a research hotspot.Firstly,this thesis analyses the background and significance of the research,and introduces the development of continuous time ?-? ADC at home and abroad.Then,the working principles of Nyquist ADC and oversampled ADC are introduced,and the theory of conversion from discrete time ?-? modulator to continuous time ?-? modulator and the principle of digital decimation filter are given.In order to satisfy the requirement of the preceding continuous time modulator,a wideband multi-mode digital decimation filter is proposed.By using different types of filter cascade structure,reasonable allocation of down sampling factors between different stages,the complexity of circuit implementation is effectively simplified,and the area and power consumption of circuit implementation are reduced.Furthermore,inter-stage filters cooperate with each other,which realize the functions of multi-bandwidth and multi-mode.According to the design indexs,the digital decimation filter system is designed and simulated by MATLAB.After the simulation meets the requirements,the register-level code design of the digital decimation filter is completed by using hardware description language,and the functional verification of the hardware implementation of the digital decimation filter is completed by calling Modelsim in Quartus II,and the simulation results show that the hardware implementation of the digital decimation filter meets the design indexs.Finally,the synthesis of the Register Transfer Level code are accomplished by DC.The designed filter is based on the 65 nm CMOS process.The simulation results indicate that the bandwidth of this filter ranges from 20 MHz to 50 MHz.With a bandwidth of 20 MHz,the corresponding ENOB is 10.64 bit,when operating in the 50 MHz mode,the corresponding ENOB is 10.48 bit.