Design And Key Technologies Of Novel Heterojuncion LDMOSFETs

As a center part of the power integrated circuit,the power semiconductor devices play important roles in power conversion and control circuit.Therefore the quality of the devices ususally determines the performance and the manufactoring cost of the chips,as well as the reliability of the circuit.Among all the power semiconductor devices,LDMOS stands out for its high breakdown voltage and easier integration with other devices and peripheral circuits.For conventional LDMOS,there is a trade-off relationship between the specific on-resistance and the breakdown voltage,so the researchers of LDMOS are focusing on increasing the breakdown volatge while reducing or maintaining the on-resistance of the devices.To further improve the performance of the devices,some researchers propose novel structures,and others choose wide bandgap semiconductor materials to design and manufacture devices.As a representative of wide band gap materials,Si C material has many advantages such as high critical breakdown electric field,high thermal conductivity,and good radiation resistance.However,the process of Si MOSFET is not completely applicable to the Si C counterpart,which resulting in some processing problems.The Si/Si C hybrid substrate offers an alternative way to solve these problems.Therefore,in this paper,two structures based on Si/Si C heterojuncion are proposed.The proposed devices can not only be fabricated by mature Si process techonology,but also have the advantages of Si C materials.The main innovations and the results are as follows:(1)A novel Si/Si C LDMOS with deep drain region is proposed.Different from the conventional Si LDMOS,the proposed structure uses a Si C substrate while the active area of the device is formed in the Si layer.Moreover,the doping depth of the device is deepened down to the Si C substrate.Therefore,the previous high electric field region around cylindrical edge of the drain is introduced into the Si C substrate.Due to the high critical electric field of the Si C material,the breakdown point will be transfer to other regions,thereby improving the trade-off relationship between breakdown voltage and on-resistance.The simulation results shows that compared to the conventional Si LDMOS,the breakdown voltage is increased from 240V to 384V with the drift region length of 20?m,increased by60%.The FOMs of the proposed structrue is improved from 2.04 MW/cm~2 to 4.26 MW/cm~2,impoved by 108%.In addition,based on the solution of the two-dimensional Poisson equation and the data obtained from the ISE TCAD simulation,this paper obtains an analytical model of the electric field and the potential distribution in the drift region.The parameters of the analytical model are analyzed to provide theoretical foundation for the simulation work.(2)A Si/Si C LDMOS with Step-Doping Drift region(SDD)is proposed.The proposed structrue is an upgrated version of the device proposed in(1).The drift region of the Si/Si C SDD LDMOS is changed from a uniformly doping distribution to a step-doping distribution.According to the simulation results,the Si/Si C SDD LDMOS has better off-state breakdown characteristics than the bulk Si SDD LDMOS.The breakdown voltage of the proposed structure is increased from 450V to 603V with the drift region length of 30?m,increased by34%.The specific on-resistance is reduced from 104.1m??cm~2 to 70.5m??cm~2,decreased by 32.3%.The optimized Si/Si C SDD LDMOS has higher breakdown voltage and smaller specific on-resistance than bulk silicon SDD LDMOS.