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Study Of The New Structure And Mechanism Of The Conductance Enhanced Lateral Power MOS Devices

Posted on:2018-04-04Degree:MasterType:Thesis
Country:ChinaCandidate:M S LvFull Text:PDF
GTID:2348330515951789Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Improving the trade-off between the breakdown voltage(BV)and the specific on resistance(Ron,sp)for lateral power MOSFET is an important topic.For low voltage power LDMOS(BV < 200 V)device,the channel resistance and the drift resistance have equally important influence on the conduction losses.The trench gate technology can not only increase the channel density but also optimize the current distribution.Therefore,the the on-state current is increased significantly and the channel resistance is reduced.High-k dielectric is introduced into the power device to modulate the electric field distribution and increase the doping concentration of the drift region(Nd),which can enhance the BV and reduce the drift resistance.Combining the trench gate and the HK technology,three kinds of conduction-enhanced lateral power MOS devices are proposed to breakthrough the “Si Limit” relationship of the LDMOS.(1)A novel SOI LDMOS with three separated gates(TSG)and high-k dielectric(HK)is proposed(TSG-HK LDMOS).The device is featured TSG and HK pillars aside the drift region.The TSGs consist of the planar gate and two segmented trench gates that extend to the buried oxide(BOX).The HK pillars and the drift region are arranged alternately in the device.In the on-state,the TSG form one plane channel and two vertical channels,so the channel density is enhanced and the distribution of the current is optimized.At the same time,the trench gate,HK pillars and the drift region constitute the MIS capacitor structure.The electron accumulation layer is formed in the drift region that beside the HK pillars,which can increase the current effectively.In the off-state,the MIS capacitance can assist in depleting the drift region to increase Nd,and thus reduce Ron,sp.Owing to the gradually decreased MIS capacitance from source to drain,the assisted-depletion effect is weaker and weaker.It generates the equivalent effect of the variable lateral doping even for the actually uniformly doped drift region,modulating the E-field and improving BV.Simulation results show that the BV is 97 V and the Ron,sp is 0.34m?·cm~2.Compared with the same size of the trench gate super junction,the Ron,sp is reduced 62%,which breakthrough the “Si Limit” effectively.(2)A novel LDMOS with double gates and ultra-low resistance current path is proposed.The device has double gates,high-k dielectric and P-pillar.The double gates include a planar gate and a trench gate.The trench gate is connected to the HK dielectric,and the N-drift region is located at two sides of the HK.The P-pillar is located at the outside of the N-drift region.In the on-state,the double gates form a planar channel and a vertical channel,which increases the channel density.The trench gate,HK and P-pillars constitute the MIS capacitor and the electron accumulation layer is formed in the drift region by the MIS,effectively increasing the current density.In the off-state,the MIS capacitor and the P-pillar assist in depleting the drift region simultaneously,which further increase the Nd and reduce the Ron,sp significantly.In the simulation,the BV is 76 V,and the Ron,sp is 0.2m?·cm~2,the FOM(figure of merit)is reached 28.9MW/cm~2.(3)A multiple accumulation layers lateral power MOS is proposed(MAL LDMOS).The device features trench gate and the HK pillars that embedded in the drift region.The bottom of the trench gate is connected with P-well,and the thickness of the HK is less than that of drift region and thus the bottom of the HK is away from the BOX.In the on-state,the inversion layer is formed in the sidewall and the bottom of the trench gate,so the channel density is increased.The electron accumulation layer(EAL)is formed in the drift region near the HK dielectric,i.e.in the sidewall and the bottom of the HK pillars.The current is greatly increased.In the off-state,the MIS capacitance can assist in depleting the drift region,which can increase Nd and improve the E-field.Therefore,the performance of the device is improved greatly.The simulation results show that the BV 126 V and the Ron,sp is 0.78m?·cm~2.
Keywords/Search Tags:LDMOS, Breakdown Voltage, Specific On-resistance, High-k Dielectric
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