Design Of FPGA-based High-performance Processor Interconnect Verification System

With the rapid development of modern society,people's demand for high-performance processors is increasing.At the same time,benefit from the continuous advancement of electronic technology and semiconductor processes,the design scale and complexity of highperformance processors have also increased rapidly.Faced with increasingly complex processor functions and structures,in order to ensure high efficiency and reliability of work,verification has become increasingly important in design work.Today,the most mature and widely used software verification technology has many advantages,including flexibility,visibility,and reusability.However,in the face of increasingly complex processor systems and shorter and shorter design period,compared to FPGA-based prototype verification technology,the defect that takes too long to verify and cannot accurately simulate real circuits is becoming increasingly apparent.Of course,the disadvantages of the traditional FPGA verification system,such as inflexible incentives and poor visibility,have been restricting its development.Based on this,this article takes a complex multi-core highperformance processor interconnect module as an example,and base on the traditional FPGA prototype verification platform,proposes a prototype verification system with flexible verification incentives and strong visibility.A separate interconnect module cannot run independently on the FPGA.This article selects the relevant master and slave module through a combination of self-development and IP multiplexing to form a complete prototype verification system.The master modules include self-developed SVIP(Synthesizable Verification IP)and Synopsys' mature single-core processor IP.Among them,SVIP uses the top-down design concept to complete the development,which can simulate the behavior of the HOST machine in the real processor system,including data transmission,reception and processing processes.The single-core processor IP is highly configurable.By configuring the necessary functions and modules,it can complete functions such as test operation,excitation transmission,and SVIP control.Moreover,the single-core processor IP has a mature HAPS prototype verification environment.It can simplify repetitive tasks such as synthesis,place and route,and test compilation,allowing us to focus on system development and optimization.In addition,this article selects SRAM as a slave device for the master device to read and write access via the interconnect module.Based on this,according to the verification requirements,this paper determines a single-core processor and multiple SVIP integration solutions as the main device and completes the system integration work.At the same time,three typical tests,Single SVIP,Multi SVIP and Memory Copy,were developed according to the characteristics of the verification system to give full play to the advantages of the verification system.Finally,this paper carried out the construction work of the specific verification environment,and completed the simulation of the verification system on the software environment and the hardware HAPS platform.In addition to having more realistic operating conditions and faster simulation speeds than software simulation,compared with the traditional prototype verification work mainly for complete processor systems,this synthesizable verification system can perform verification work on individual interconnect modules,which can effectively shorten the development cycle.Compared with traditional HOST machines,the SVIP can not only reduces FPGA resource occupation,but also has the advantages of flexible and controllable incentives.At the same time when the hardware simulation is carried out on the HAPS platform,the use of Meta Ware tool and DTD technology also greatly improves the visibility of the verification system when carrying out prototype verification work.In the end,all three tests passed,which proved the correctness of the system;the running speed on HAPS was also significantly faster than software simulation,especially the time for Memory Copy Test was shortened from 9 hours,48 minutes,24 seconds to 4.85 seconds.It also fully reflects the huge advantage of prototype verification in speed.