Verification Of Key Modules Of ARC HS Processor Core

With the rapid development of embedded processors in recent years,the design scale and complexity of embedded processors are increasing.How to verify the processor core accurately and efficiently is one of the hotspots in the current verification field.Based on Synopsys company resources,this thesis aims to verify the function of DDR controller module and floating-point operation unit module in a HS series processor core of Synopsys company.At the same time,the system-level function and performance of the processor core are verified.Mainstream verification methods include software verification and hardware verification.Considering the need for system-level function/performance analysis of the processor core,the test incentive algorithm is complex and the amount of computation data is huge,and the efficiency of hardware verification is usually 1-6 orders of magnitude higher than that of software verification,it is decided to adopt hardware verification method and choose the type of HAPS-80S26 as hardware in combination with company resources.The prototype verification method of FPGA is used as a specific verification method.For module level verification,gray box verification mode is used to extract the corresponding verification function points.Test incentives are generated by combining random test vectors constrained with fixed test vectors under tightening constraints.The results are analyzed by comparing the two inspection mechanisms of standard model and functional coverage check.In view of the verification scenarios required for system-level verification objectives,EEMBC system test suite is selected as the main system-level function and performance verification incentive,and the inspection mechanism includes normal execution of test procedures and self-detection of results.At the same time,the Linux operating system running on an HS processor core is used as system-level application verification to further verify the correctness and stability of the processor core.Based on the verification objectives,verification schemes,verification environments and incentives,this thesis discusses the five parts of an HS processor core structure analysis,verification objectives and verification schemes,the generation of processor core verification prototype through code migration operation,the construction of verification environment,and the analysis of specific verification results.After code transplantation,the clock frequency of an HS processor core is set to 50 MHz,and the worst set-up time sequence and maintenance time sequence margin are 1.365 ns and 0.041 ns,respectively,to meet the timing requirements.The actual resource occupancy rate of the FPGA is less than 50%.The total power consumption is 0.772 W,the dynamic power consumption is 0.126 W and the static power consumption is 0.646 W.The verification results show that the FPU and DDR controller modules of floating-point operation unit are functionally normal,and the verification coverage of the extracted verification function points reaches 100%.The EEMBC benchmark test suite program can be executed normally,and the results of the calculation have passed the result self-detection mechanism test.The overall function of the HS processor core is correct.The main Core Mark test item score in the test set is Core Mark/MHz 1.0:1.173279/GCC4.2.1-O6/STACK,which shows that the performance of an HS processor verified in this thesis is at the median level in the whole series of HS processors.HS processor core can run Linux operating system normally.The verification results show that the design idea of the prototype verification platform of the FPGA is correct.This thesis successfully completes the verification of the intended verification target.