Low Power Implementation And Optimization Of LPDDR4 Memory Controller

In recent years,with the development of technology and the improvement of people's demand for quality of life,portable mobile electronic devices with high performance and strong endurance have increasingly appeared in people's daily lives.During the working process of the mobile device,a large amount of data is required to be accessed by the memory and the processor module.Therefore,the memory controller,as a medium for data transmission,plays a vital role in the entire system.At the same time,the advancement of semiconductor technology processes and the optimization of digital integrated circuit design methods have increased the complexity and integration of chip circuit design,which will cause the overall power consumption of the chip to continue to rise,which will bring the performance and reliability of the chip.How to achieve low power consumption on the premise of meeting chip performance has become a key concern of chip design.This article mainly focuses on the analysis and research of the power consumption of the LPDDR4 memory controller in the idle state.The main research object of this article is the LPDDR4 memory controller,which is mainly responsible for the data exchange between external modules such as memory and processor.With the continuous development of integrated circuit design technology,memory is constantly updated,performance is constantly improved,and the performance of modules such as processors is also continuously improved.In order to improve the data transmission efficiency between the memory and the processor,the memory controller also needs to continuously improve its data transmission performance to match the high-performance memory and processor.With the improvement of the performance of the memory controller,the power generated by the module has increased significantly.High power consumption will cause the internal temperature to rise,causing problems in the performance and reliability of the memory controller.In order to meet the demand for high performance and low power of the memory controller,low power design is needed in the circuit design process of the memory controller.Although the LPDDR4 memory controller studied in this article has a low-power operation module,in actual project applications,the low-power operation cannot meet the application requirements.Therefore,further power optimization of the LPDDR4 memory controller is needed.When the LPDDR4 memory controller is idle,power analysis and optimization are performed from two aspects,the RTL level and the Gate level.First of all,introduce the sources of power consumption in integrated circuits and power optimization methods at different levels of abstraction.Then briefly explain the development and working principle of the memory,and analyze the working principle and circuit structure of the LPDDR4 memory controller.Secondly,the power consumption is optimized according to the working principle and circuit structure of the LPDDR4 memory controller.At the RTL level,the power consumption is optimized for the clock signal,and at the Gate level,the power consumption is optimized for the clock tree.Finally,based on the comparison of the simulation data before and after the optimization,it is found that the power consumption is optimized about 48% at the RTL level and about 26% at the Gate level.The simulation data is compared with the actual chip test data to confirm the actual power optimization effect.This module belongs to the project of Intel.Through the power consumption optimization described above,the power of the module is significantly reduced in the idle state.