Key Research Of Low Power On Chip Bus For MPSoC

This article comes from the project of Network Processor which is one of the projects of National Integrated Circuit Talent Base , school of Microelectronics and Solid State Electronics of Xidian University .This article is mainly talking about the design of OCB(On Chip Bus) and bus interface of low power MPSoC .This article researches the performance require of XDNP network processor's OCB , finishing the design method of bus structure in system controlling level , with researching the function of system bus and mapping between different modules in XDNP network processor . This article realizes the system bus and memory controller interface , according to the AMBA 2.0 specification and the system bus realized in this article is the subset of AMBA 2.0 specification . This article finished the RTL design of arbiter,decoder,mux of XDNP system bus with fully understanding the AMBA 2.0 specification , using the ModelSim to finish function simulation ; with inserting the gate clock and using the method of encoder / decoder of address bus no-changed ; using Prime Power to finish the power analysis and compare the results . Based on the project aim , this article finished the RTL design of memory controller interface , which connects the system bus and memory controller, researching the address mapping of memory controller interface and finishing function simulation using ModelSim . This article designs one 32 bits RISC , based on fully understanding of ARMv4 architecture ,building SoC verification platform to verify the function of XDNP system and memory controller interface . Using Design Compiler to synthesis and optimize the two designs in this article .This article finished the RTL design of XDNP network processor's system bus and memory controller interface , which connects the system bus and memory controller ,finishing the function simulation , synthesis and optimization , the results show that the two designs in this article meets the stated requests .