Method Research On Performance Analysis And Optimization Of SoC System Based On LPDDR4 Controller

With the advent of the mobile terminal era,SoC technology has been more widely applied and developed.In order to meet users' increasing functional requirements for mobile terminal products,more and more processor subsystems and IP cores are integrated in SoC chips.How to improve the overall performance of the SoC to the maximum extent on the basis of ensuring the normal cooperation of the various subsystems will directly affect the user's favor for the product.For this reason,SoC chip designers need to receive feedback from the chip performance evaluation data as early as possible in order to complete the optimization and improvement of the overall performance of the SoC system within the market window of the product.However,most of the current SoC-based performance analysis and testing is performed after the chip is taped out,so it is impossible to provide chip designers with timely and effective performance data,and it is easy to lose costs due to failure to perform performance test after taped out.As for the performance analysis before chip tape-out,the industry has not yet formed a unified and complete standard and specification.At present,the commonly used pre-silicon performance analysis methods such as model building and dynamic simulation are also caused by insufficient accuracy or low efficiency.The system performance analysis is incomplete.Based on the idea of SoC chip function verification,and by drawing on the performance analysis method of dynamic simulation before silicon,this paper proposes a set of efficient performance analysis schemes for LPDDR4 memory controller system.This solution first analyzes the architecture and data path of the memory controller system,and gives performance indicators to measure system performance and performance optimization goals.Then based on the analysis of various performance optimization logics inside the memory controller system,all software configuration parameters and hardware design parameters that affect the performance of the system were extracted.Then focused on developing an automated performance testing environment for performance verification of these performance parameters.This environment not only integrates a UVM verification platform that can be used for dynamic simulation of test cases,but also integrates automated performance analysis tools based on Python.Then applied this efficient automated performance test environment and the module-level test cases written to simulate SoC multi-port data transmission,and completed the performance analysis and optimization of all software configuration parameters and hardware design parameters in the memory controller system.The influence of these parameters on the performance of the memory controller system,and through feedback with the chip designer,the software configuration of the memory controller system under different data transmission scenarios was finally improved,and the hardware design that affected the system performance bottleneck was repaired.Based on the proposed automated performance analysis scheme,this paper fully analyzes the key designs that affect the performance of the system,extracts all relevant hardware and software parameters,develops an automated performance verification environment,and completes the performance completeness verification of all relevant parameters,while improving the efficiency and automation level of performance analysis and finally make the overall performance of the SoC system significantly improved.Among them,among the four SoC subsystems participating in performance evaluation,the average CPU throughput increased the most,reaching 119.4%,the average throughput of OCH also achieved a 11.9% increase,and finally the total throughput of the four subsystems was achieved 28% overall performance improvement.In addition,after the optimization,the average delay time of the four subsystems when performing data transmission at the same time also achieved a performance improvement ratio of more than 35%,of which the CPU improvement ratio was the largest,reaching 41.7%.The statistical distribution of the overall delay time of the system showed a significant left shift.The delay time value with the largest number of statistics changed from 210 ns before optimization to 120 ns after optimization,and the performance improvement ratio was 42.9%.