| With the increasing requirement of external bus bandwidth,PCIe bus protocal is proposed to replace the traditional PCI bus.Compared with PCI bus,PCIe bus changed from parallel interface to serial differential interface,which effectively reduced the number of pins.PCIe bus also embedded the clock in the serial data,making its transmission rate higher.In addition,the PCIe interface is an end-to-end topology,and the number of channels in its link can be multiple,so its transmission rate can be increased by several times.With the improvement of bus interface performance and chip complexity,the traditional Verilog based verification platform can not meet the actual verification requirements.The emergence of system Verilog language,combined with some advanced methodology,provides a better solution to meet the verification requirements in the current chip design environment.Compared with Verilog,SystemVerilog has the characteristics of object-oriented programming.It introduces the concept of class which has the characteristics of inheritance,polymorphism and encapsulation.So that user can build a verification platform at a higher level of abstraction.Its transaction level verification technology can greatly improve the efficiency of chip verification and shorten the development cycle of the chip.Therefore,this paper chooses SystemVerilog to build an verification platform.The chip verified in this paper is a PCIe bridge chip.One end of the chip is connected to PCI / PCI-X device,the other end is connected to PCIe device.Upstream device and downstream device can be changed according to different configurations.The chip is used to convert PCI bus and PCIe bus,so as to realize the compatibility of new PCIe devices with old PCI devices.Firstly,the functional specification of the PCIe bridge chip and PCI,PCI-X,PCIe protocol are studied in this paper.Based on this,the verification strategy is formulated and the corresponding function points are extracted.Then,the system Verilog is used to build the verification platform for the function points to be verified.The verification platform includes the modules such as initiator,monitor and checker.It also combines the PCIe,PCI / PCI-X bus VIP.In order to ensure the completeness of verification and make the chip free of bugs,relevant test cases based on the extracted function points are needed.And then the integral verification platform is used to carry out a comprehensive verification of the chip.All function points are simulated and verified according to the sequence.When bugs are found,they are accorded.After the circuit is modified,regression test is carried out.And finally coverage is collected after all function points are verified to ensure the completeness of verification.The transaction level verification platform built by SystemVerilog has the characteristics of high efficiency and easy maintenance.Using the constrained random stimulation in SystemVerilog,the convergence rate of coverage is improved compared with the traditional orientation test.And the verification platform built can be reused after slight modification in subsequent projects,which shortens the time of verification work and saves resources.The final function coverage rate reaches 100%,and the code coverage rate exceeds 97.83%,which meet the requirements of the design specification. |
