Research On Transaction Level Template Modeling Method Of Hierarchical Platform-Based SoC System

The high speed development of Integrated circuit technique brings an opportunity for the development of System-On-a-Chip (SoC). However, with the fast exaltation of chip integration, SoC's design scale and design complexity enlarged continuously, but the corresponding design capability evolved very slow, which makes SoC designer face a serious difficulty and challenge because of the contradiction of design and manufacture. For solving this kind of predicament, we need to put the hardware/software co-design technique in high level and Platform-Based reuse technology together to set up a new hardware/software co-design platform of SoC in high level.A Hierarchical Platform-Based Design (Hi-PBD) method for SoC hardware/software co-design was present in the last few years. This method divides the high level design flow of SoC system into three levels (i.e. System Modeling Level, Transaction Level and Register Transfer Level). On the hierarchical platform, software design and architecture design can proceed in parallel, hardware/software co-simulation can be executed as early as possible, hardware/software co-design can be handled through refining, mapping, simulation and constraint propagations, the high reuse of former module and architecture template can be support in the platform to lower the time-space consumption and improve design speed and design quality.In this paper, we deeper researched the more complicated Transaction Level Template Modeling method of Hierarchical Platform-Based Design. The main work and achievements are as follows:1) We advanced a Template modeling method based on CCST (Computation Communication Scheduling Template) process in SoC Transaction Level. In the process, computing module, topology, bus protocol, arbitration mechanism, job scheduling of SoC system are abstracted and classified by function, communicated and scheduled in transaction level. These factors would be designed and verified respectively, and then be crossly coupled to constitute the whole system, thus simplified the design of SoC system in Transaction Level, accelerated the exploration in platform's design space.2) We advanced a Template simulation method based on VMS (Virtual Middle Socket) in SoC Transaction Level. With the purpose of simplifying hardware/software refining process and accelerating hardware/software co-simulation, the method uses collaborative work of socket communication unit, data convert unit and cycle scanning unit to complete the function verify process and performance estimation process in transaction level, then provide the feedback information for hardware/software dividing and function mapping.