The FPGA Design For Radar Signal Preprocessing

With the development of radar technology,the number of channels,working mode and front-end AD sampling frequency of airborne radar are increasing.The traditional algorithm structure and data processing sequence are not suitable for high-speed and massive echo data streams.The high-speed transmission of data between boards,the stable storage of pulse data within the board and the real-time processing of multi-channel echo data become an important part of radar signal processing system.According to the above requirements,a preprocessing board is designed in this thesis,which uses FPGA main control chip to complete the radar signal preprocessing process of multi-mode,multi-channel and multi pulse accumulation.In this thesis,firstly,the principle and implementation structure of digital down conversion,pulse compression and moving target detection algorithm are studied,and a radar signal processing platform based on Open VPX standard is designed according to the project requirements.At the same time,the SRIO high-speed internet is built.The 4×link rate can reach 16Gbps,and the throughput is high.It is suitable for multi-channel radar signal processing system composed of multiple signal processing boards.Then a set of detailed engineering preprocessing implementation scheme is given.A two-stage decimation structure is designed to complete digital down conversion,which solves the problem of multi-mode and multi-channel processing occupying too many multipliers and memory resources,and realizes real-time switching of multiple sets of filter coefficients.Multi-channel data pulse compression is realized in the way of even and odd two-way parallel processing,and the results are spliced and written into DDR3.The processing speed of this method can reach twice that of conventional channel-by-channel processing.Aiming at the problem that two groups of DDR3 ping-pong operations occupy a large amount of FPGA high-performance I/O resources,a solution is proposed and implemented in which a single group of DDR3 divides two spaces for ping-pong operations.Next,the data reading scheme of DDR3 bandwidth utilization and cache space balance and the high-speed implementation of two-way moving target detection are given.The timing problems and corresponding solutions encountered in the FPGA logic design process are introduced.Finally,the communication interfaces for data interaction between the pre-processing board and other boards are designed.Aiming at the problem of data skew in serial transmission,two schemes are designed,which are high sampling rate for sampling intermediate value and delay training DPA,with high stability.They are respectively used in low-speed serial port and high-speed LVDS interface.Using QSFP and GTH transceiver to complete the design of 20 channel echo signal receiving module,the small volume and high bandwidth QSFP interface and serial communication transmission mode greatly reduce the difficulty of PCB wiring.In the way of DOORBELL synchronization,the SRIO transmission flow between four signal processing boards is established and the pre-processing results are sent in the form of high bandwidth SWRITE.The preprocessing scheme designed in this thesis is based on the Open VPX hardware platform,using FPGA as the main control chip,cooperates with DDR3 SDRAM,serial port,LVDS interface,QSFP optical module and backplane SRIO to complete the high-speed processing of multi-channel radar echo data.It has the advantages of less occupation,fast algorithm processing speed,and strong data transmission stability.Matlab is used to verify the results of FPGA preprocessing algorithm,the relative error accuracy is on the order of 10^-4,and each transmission interface of preprocessing board is debugged for many times,the data reading and writing test is stable,meeting the needs of the project.