Design Of Fourth-order High Precision Sigma-Delta ADC

With the development of CMOS technology,the performance of digital circuits has been improved rapidly.Process deviation,device mismatch and temperature characteristics still restrict the performance of analog circuits.Sigma-Delta ADC is the most rapidly developed and widely used mainstream technology in recent years,which introduces the oversampling and noise shaping technology,improves the accuracy by sacrificing the working speed,breaks through the limitation of matching error and reduces the difficulty of design.This paper first studies the development of Sigma-Delta ADC from its emergence to becoming the mainstream technology,as well as the research status of its structure and performance in recent years,and analyzes and compares the advantages and disadvantages of common structures.According to the required performance index,the system level design of Sigma-Delta ADC is carried out,and the basic implementation scheme of the design is established.The fourth-order single loop single bit quantized full feed-forward modulator structure is selected,and the oversampling rate is 128.The system level model of the corresponding structure is established,and the feedforward,feedback and integral coefficients in the model are determined.The structure of decimation filter is designed as five order CIC filter,fir compensation filter and half band filter.The system level model of Sigma-Delta ADC is simulated and analyzed.Based on the system level modeling results,the circuit level design of Sigma-Delta modulator is completed.The modulator is a discrete-time modulator.The overall circuit structure is realized by a fully differential switched capacitor circuit.Its internal sub modules include an integral unit,a feedforward summation unit,a dynamic comparator unit CMOS complementary switches with virtual transistors are used in the integrator.A single-stage folded cascode structure with common mode feedback(CMFB)is used in the fully differential operational amplifier.A chopper structure is added to the first stage integrator to reduce the influence of low-frequency flicker noise.This design uses 0.35?m CMOS technology to realize the Sigma-Delta modulator circuit,and completes the layout design and post simulation verification.The area of the layout is 1750×840?m~2.When the input signal frequency is 1k Hz and the amplitude is 1V,the output SNR of the modulator is about 94.55db,the ENOB is 15.4 bits,and the harmonic distortion is-102.3db.After digital filter processing,the output SNR is about91.9db,and the ENOB 14.98 bits.