Design Of The Low-Power Chopper Sigma-Delta Modulator

In the modern social world, digital area speeds up rapidly. As the bond between the digital world and analog world, analog digital converter(ADC) is quiet crucial. A DSP system could not conduct a continuous-amplitude and continuous-time constant without an ADC. What made it develop so fast is that people exploit a lot in the ADC area according to the significance of ADCs. Oversampling technique promote the precision of ADCs, made it more and more popular in the applications. Modulators and digital decimators are concluded in ADCs. The basic quantization is accomplished by the modulator.This paper presents a single-loop 4th–order full-forward Sigma-Delta modulator. A full-feedforward topology drops the limitations for the input signal amplitude. Full-differential OTA is completed with switched-capacitor common-mode feedback circuits. For a better linearity, 1-bit quantizer is picked to fulfill the circuits. The clock system is non-overlapped. The bandwidth of the input signal is 200 Hz. To annihilate the flicker noise at low frequency, chopper-stabilized structure is applied in the first integrator.The system-level simulation in this paper is under the construction of SIMULINK. To get the parameters of the modulator, I gather the designed model of the partial circuits and conduct the system-level simulation. Transister-level design is under the construction of CADENCE. The layout of the integral circuits is also fulfilled under the construction of CADENCE using the Shanghua 0.5um CMOS process. With the bandwidth of 200 Hz, I simulated the integral circuits. The results manifest that the noise floor of the PSD is-120 d B and the SNR could be 103 d B. The ENOB is 16.83 d B.