The Design Of High-accuracy Multibit Sigma-Delta Modulate In TMR Sensor

With the development of modern communication technology, Domestic system technology has been greatly improved, but some core wafers still have a lot of room for improvement such as high speed and accuracy analog-to-digital converter(ADC).In practical applications, ADC is so important that the research and design of it becomes hot. The most important part in sigma-delta ADC is modulator, and it decides the accuracy and speed of ADC. After much study and research, this paper designs a 4th-order, 3-bit quantization sigma-delta modulator with local negative feedback and negative feed-forward in the structure of CIFF. Theories about sigma-delta modulator is introduced firstly, secondly non-ideal factors are analyzed and modeled based on Simulink, thirdly transistor-level circuits are designed and simulated, finally layout is completed and post-simulation is carried out.The model of sigma-delta modulator is established based on Simulink, the SNR of modulator is 140.7dB, ENOB is 23.08 bits and harmonic distortion is-120 dB with 6.4MHz sampling frequency, 128 over-sampling ratio in the ideal case. Considering the non-idealities, the model is re-established. In the same simulation conditions, the SNR is 120.5dB, ENOB is 19.7bits and harmonic distortion is-110 dB with 0.1% mismatch.The structure which is insensitive to parasitic capacitor is adopted to design the transistor-level circuits. The amplifier in the first integrator is implemented with gain-boosting folded cascode structure and chopping. Because of the multi-bit quantization, analog adder must be designed in order to attain precise summation. To further improve the speed of quantization, Flash structure and pre-amplificative comparator with four input are in use. The switch is provided with CMOS with virtual tubes to reduce nonlinearity and charge injection. Data Weighted Averaging(DWA) is designed with Modelsim to reduce the effect of the mismatch. Finally, the proposed sigma-delta modulator is simulated under the circumstance of SpectreVerilog in Cadence, the SNR is 125.4dB, the ENOB is 20.53 bits, and the harmonic distortion is-121 dB.The analog layout is drawn in the use of 0.35 ?m 5V standard CMOS process. The verilog code of DWA is synthesized and generates digital layout. Post-simulation is executed, the SNR of the designed modulator is 121.3dB, the ENOB is 19.85 bits, and the harmonic distortion is-113 dB.Performance of the modulator has reached the requirements of the index.