Design And Error Analysis Of High-resolution SRAM Timing Parameter Measurement Circuit

With the development of integrated circuit technology,the performance of SRAM is increasingly enhanced.In order to maximize the SRAM performance of computer,the timing parameter needs to be measured precisely and the auto-testing machine needs to achieve picoseconds level.Obviously,it is hard for machine to achieve this accuracy level and would cost a lot to achieve so.How to accurately measure the SRAM timing parameter becomes one of problems faced by researchers.The paper firstly introduced the on-chip measurement circuit scheme,time-digital converter.Centered on the converter,the structures of converters are further categorized and the delay element are summarized based on the current research results.Then,the paper raised a TDC circuit that carries self-calibration function based on the delay chain with both coarse and fine tuning delay unit adjustment functions,which do not only save the squire cost,but also speed up the measurement speed.In order to realize the automatic conversion measurement between the different portals of SRAM and timing parameters including set-up time,hold time,and reading time.This paper also designed an SOC system that integrates the CPU,UART,SPI,AMBA,measurement circuit,and SRAM to be measured.Through UART and SPI module,the controlling instructions are inputted;through CPU controlling,measurement configuration register is inputted.Through reading the data of configuration register,the measurement circuit realized the automatic measurement.Finally,the paper carried out error analysis on the measurement circuit and reached the minimum resolution of6.5 ps.The error ranged from 26 psto 47ps with the measurement varying from 200 ps to 2ns.