Analysis, optimization, and modeling of CMOS circuits incorporating variable supply voltage and adaptive body bias

Fixed-supply-voltage/fixed-threshold-voltage, variable-supply-voltage/fixed-threshold-voltage (VSV/FTV) and variable-supply-voltage/variable-threshold-voltage (VSV/VTV) are three CMOS design approaches which affect both circuit speed and energy-efficiency. Threshold voltages are varied by changing transistor body-bias terminal potentials.; Measured energy and performance of three corresponding embodiments of an existing 32-bit digital multiplier design, fabricated in 0.35 mum technology, show that for the same speed an optimized VSV/VTV implementation reduces circuit power dissipation by more than 5:1. VSV/VTV operates without error at a clock frequency of up to 38 percent faster than a functionally equivalent VSV/FTV implementation. Low-voltage operational range depends directly upon satisfying certain minimum IonNMOS/I offpMOS and IonPMOS/I offNMOS values and is extended from 0.48 to as low as 0.16 V by appropriately balancing transistor thresholds.; Two control approaches that dynamically adjust both the supply voltage and the body-bias voltage to optimize the balance of active power and leakage power, while maintaining a guaranteed performance rate, enable widespread usage of VSV/VTV technique. Embedded speed sensors track the circuit speed, and either (i) an Ion/I off circuit or (ii) a well-voltage perturbation controls the transistor threshold voltages; implementation of (i) is simpler, but the (ii) is more universally applicable. Simulations of both algorithms converge within 6 percent of the absolute minimum power for the required performance, in the absence of any measurement errors and speed guardbands. The introduction of a speed guard-band of only five percent increases the power overhead to 20 percent.; A numerical model enabling relative design comparisons in terms of speed and energy per operation among the three design techniques accounts for average logic depth, circuit activity, local and global transistor variations, chip yield, and temperature. It simulates per-die adaptive supply and threshold voltages. For a 32-bit-multiplier design running at 138 MHz, i.e. , the maximum speed of an example CMOS implementation, the model predicts that the VSV/VTV approach is about one third more energy-efficient than the VSV/FTV approach with an optimal fixed threshold voltage.