Design Of A High Linearity CMOS Analog Multiplier

To improve the performance and speed of digital integrated circuit,the area and power consumption of the integrated circuit is usually increased.The area and power consumption of the whole integrated circuit will be reduced if the analog signals can be processed directly.Quadrantal analog multiplier plays an important role in modern signal processing system,and which is widely used in artificial neural network,phase-locked loop,frequency conversion mixer,adaptive filter and other signal processing systems,and so it is very important to study quadrantal analog multiplier.Firstly,the design techniques of analog multiplier in domestic and abroad were investigated,and then the advantages and disadvantages of these design techniques were analyzed.Secondly,the basic concept,the working principle and the application of the analog multiplier in related fields were discussed.Thirdly,a CMOS four-quadrant analog multiplier was proposed based on Gilbert analog multiplication unit,an active attenuator is used to attenuate the input signal and to improve the signal processing capacity of the multiplier,a source follower was used to translate the voltage of the signal and the signal was preprocessed so as to improve the performance of the multiplier.The circuit is mainly composed of an active attenuator,a CMOS Gilbert multiplication unit and a bias circuit,the input signal was attenuated and the voltage was transformed by the attenuator,the preprocessed signal was multiplied by the CMOS Gilbert multiplication unit and the bias voltage for the current source was provided by the bias circuit.The whole circuit was designed with TSMC 0.18?m technology and was simulated using HSPICE software.The simulated results were proposed when the power supply voltage was 1.8 V and the input range was ±0.6V.The nonlinear error of the analog multiplier was 3.84%,the-3 d B bandwidth of X port was 181 MHz,the-3 d B bandwidth of Y port was 215 MHz,the equivalent input noise was 287 n V/ Hz,the equivalent output noise was 9.83 n V/ Hz and the dynamic power consumption was about 4.176 m W,respectively.The layout of the analog multiplier was designed optimally at last.Compared with other analog multipliers in the literatures,the nonlinear error in this paper was very small in the case of wide input range and high frequency signal can also be processed,and so this analog multiplier can be applied in wide input range and high frequency analog signal processing system.