The Research And Design Of Low Voltage Low Power CMOS Analog Multiplier

In recent years,with the rapid development and popularization of battery power portable electronic products , the demands for their performances are more and more high. As the development of the battery technology is far beyond the IC and electronic systems, analog circuits that can operate at low voltage to reduce power consumption are urgent required. Thus, low voltage low-power analog circuit design techniques are becoming research hotspot.The analog multiplier circuit is one of the important building blocks in VLSI communication systems, which can be applied to frequency mixers, variable gain amplifiers, adaptive filters, phase-locked loops and much other signal processing circuit. Therefore, the research on the design of low-voltage low-power analog multiplier is very necessary.The thesis firstly has done the widespread investigation and study to the domestic and foreign design technologies of low voltage low power analog circuits , and analyzes the advantages and disadvantages of these technologies; Secondly it introduces the basic concepts of analog multiplier, multiplication method and applications. Finally, based on MOSFET operated in the saturation region, two basic sub-circuits used by low voltage low-power analog multipliers - parallel coupling cell and subtraction cell are proposed, and the paper has done some analysis to the multipliers composed by the two cells and gives the comparison between them. And by taking the advantages of these kinds of multiplier circuits, a novel compact low-voltage low-power four-quadrant analog multiplier circuit is presented.The proposed multiplier was designed and simulated in HSPICE using standard model parameters for .18μm CMOS fabrication process. Simulation results show that, when operated under a 1.5V single supply, the proposed multiplier consumes 0.27mW of quiescent power, its linear range with respect to both differential input voltages is±0.4 V and its -3dB bandwidth is about 1.5GHz. By using MATLAB for Fourier analysis, we can observe that the largest harmonic component (third harmonic) of the output voltage spectrum is about 30dB below the fundamental component when input signal was a 2-MHz sinusoidal. The proposed multiplier features low-voltage operation, very low quiescent power consumption, high-linearity and high operating frequency. In comparison with previously multiplier circuits, under the same static power consumption and supply voltage level of 1.5V, the proposed circuit exhibits better linearity. This circuit is accepted to be useful in low voltage low power high linearity analog signal-processing systems.