Architectures and circuit design techniques for ultra low voltage CMOS receivers

In this thesis, we explore the design and implementation of integrated receivers for wireless communications operating from ultra low voltage (ULV) supplies from 0.5 to 0.6V. We address the design challenges in receivers both for wireless personal area networks (WPAN) as well as for wide-area cellular networks. We present three receiver prototypes---(i) a 2.4GHz sliding-IF receiver operating from 0.5V, (ii) a highly integrated 2.4GHz dual-mode, zero/low-IF receiver operating from 0.6V and (iii) a 900MHz zero-IF receiver with in-band feed-forward interference cancellation operating from 0.6V. The sliding-IF receiver and dual-mode receiver are targeted for WPAN applications; and the direct conversion receiver with in-band feed-forward interference cancellation is targeted for cellular communications.;The first receiver uses a sliding-IF topology and extensively relies on RF and IF passive components like on-chip inductors to achieve its low voltage operation. It further contains a 5th order Chebyshev leap-frog low-pass baseband filter on-chip to provide final channel filtering. The 0.5V sliding-IF receiver prototype in a standard 90nm CMOS technology achieves a conversion gain of 31dB, NF of 18dB and IIP3 of -22dBm, with a power consumption of 8.5mW and occupies 3.4mm2. Whereas this receiver achieved a benchmark performance in terms of low voltage operation, its FoM was lower than comparable receivers operating from higher supply voltages. The dual-mode, zero/low-IF receiver uses current-domain signal processing in the RF mixers and introduces a baseband architecture that merges the variable gain and filtering function using biquads; both techniques were demonstrated to significantly improve linearity performance for ultra low supply voltage operation. This receiver achieves a conversion gain of 67dB, NF of 16dB and IIP3 of -10.5dBm which is compatible with a commercial WPAN standard like Bluetooth or Zigbee. The receiver prototype also has an on-chip frequency synthesizer, consumes 32.5mW and occupies an area of 2.9mm 2 in 90nm CMOS. Its area is significantly smaller than the sliding-IF receiver, given the higher level of functional integration, and it achieves a 10-fold improvement in FoM.;The performance of both designs remains limited by a fundamental trade-off between NF and linearity that degrades when supply voltage and available signal swings reduce. In the third ULV receiver, a novel feed-forward interference cancellation architecture is demonstrated that cancels the interferers in the current-domain baseband output of the RF mixers before they are converted in voltage signals and impose linearity and gain limitations; the proposed solution offers a significant improvement over earlier cancellation solutions especially for ultra low voltage operation and breaks the fundamental performance trade-off present in earlier designs. The 900MHz receiver operates from 0.6V, achieves a conversion gain of 55.2dB, a NF of 6.2dB and an IIP3 of -8.6dBm, consumes 26.4mW and occupies 2.56mm2 in a 65nm CMOS process. This combination of low noise, high linearity and low power meets the requirements of a commercial cellular standard like GSM. Its FoM is 10-fold better than the dual-mode receiver and is on par with the best published receivers operating from higher supply voltages. The architectural and circuit design techniques demonstrated in this thesis enables the realization of high performance wireless receivers in future CMOS processes. (Abstract shortened by UMI.)...