Research And Design Of Frequency Multiplier Based On CMOS Procress

With the continuous development of science and technology,in order to meet people's needs for daily lives,mobile communication technology has developed rapidly.CMOS integrated circuit has the advantages of high integration,miniaturization and low cost.CMOS integrated circuit is widely used in communication,radar,civil and military fields.With the increase of the working frequency of mobile communication system,it is more and more difficult to build an oscillator with low phase noise.In order to solve the problem,it is important to study the frequency multiplier with nonlinear devices.The frequency multiplier of CMOS process can get the high frequency signal with high spectral purity by doubling the low frequency input signal to the high frequency output signal.This paper mainly focuses on the research and design of frequency multiplier in CMOS technology communication system.The research direction of this paper includes four main parts:One,introduce the theory knowledge of frequency multiplier.Starting from the nonlinear devices,this paper introduces some nonlinear devices used in the frequency multiplier and the realization principle of the frequency multiplier,and further introduces the frequency multiplier theory by analying the frequency multiplier using the field effect transistor.Two,for the passive devices-passive inductance,passive capacitance,transformers,simple research.At the same time for the fourth order transformer matching network is analyzed,introduces how to use the transformer to design the broadband impedance matching network,provides the basis of impedance matching for the design of the broadband double frequency,and introduces several techniques to improve the conversion gain and harmonic suppression of the frequency multiplier.Three,a high harmonic suppression broadband double frequency introduction.For communication system applied in 5G a degree channel of high harmonic suppression of broadband double frequency design.The output frequency range is 16?26GHz,the conversion gain is greater than 0.4d B,and the fundamental suppression is greater than35 d Bc.In view of the high degree of harmonic suppression index requirements,the design adopts the traditional Push-Push double frequency structure.In order to improve the conversion efficiency,we can use the Load-Pull technique to determine the optimal Load impedance.In order to solve the low frequency structure of common source of input impedance matching,which is difficult problem,we starting from the model of the MOS tube,by using the parasitic capacitance of the MOS and grid series inductance matching the way of input.In order to further increase the output power of the double frequency,a buffer is cascade to increase the output power is in the behind of the double frequency stage.Four,a high degree of harmonic suppression tripler.The output frequency range is18?24GHz,the conversion loss is less than 9.7d B,the suppression of the fundamental is greater than 17 d BC,the suppression of the second harmonic is greater than 16.5d BC,the suppression of the third harmonic is greater than 20.5d BC.Using double balanced structure can effectively improve the inhibition to the fundamental wave.At the same time,we use the transformer barron to parasitic capacitance of the MOS coupling,the mixing of dc pathways and Push-Push dc separate pathways,to improve the conversion efficiency of frequency multiplier,and through reasonable double balanced mixer circuit layout design to achieve more balanced signal input and output.Both input impedance matching and out impedance matching adopt the fourth order transformer matching to achieve broadband impedance matching.