Empirical study of the effect of cell granularity on FPGA density and performance

Field Programmable Gate Arrays (FPGAs) are VLSI chips that can be electrically customized in a matter of minutes on the designer's desk top. These chips are becoming increasingly popular for system prototyping as well as for low volume production. They are also finding applications in novel reconfigurable computing subsystems.; The extra circuitry and wiring needed to make an FPGA field programmable increase its area and delay as compared to conventional custom or semi-custom VLSI. Careful design of the FPGA architecture can help reduce this difference. The appropriate architectural trade-offs are, however, difficult to determine analytically because of the complex interactions of the processes of logic synthesis, placement, and routing with the FPGA architecture. Accordingly, we developed an architecture evaluation workbench which can be used to systematically investigate the effects of varying architectural and technology parameters on the density and performance of an FPGA. Using this workbench, an FPGA architecture can be tuned or "optimized" for a given set of applications and technology parameters.; A crucial choice in the design of an FPGA architecture is the type and granularity of its basic cell. In this dissertation we present empirical results obtained using our architecture evaluation workbench which demonstrate the effects of varying cell granularity on FPGA density and performance. We show how the "optimum" cell granularity is related to various technology parameters. We also present partial analytical models which support the empirical findings. The results should prove useful for developing denser and/or faster FPGAs.