| Field-Programmable Gate Array (FPGA) has become one of the key digital circuit implementation medias over the last two decades for its unique reconfigurable technology and other merits. A crucial part of its creation lies in its architecture, which has a dramatic effect on the quality of the final device’s speed, area, and power. Among the several parts of FPGA architecture, programmable routing resource costs60%～70%of the chip area and signal delay.Firstly, the programmable routing architecture of0FDP2009FPGA chip designed by our lab has been introduced in this article and the weakness of it is pointed out:Conventional FPGAs use transistor switch in short range interconnection and bidirectional mid range lines, which would make the interconnection delay grows exponentially with the wire length as the number of Look Up Table(LUT) in CLB increases.Then we present an improved high performance routing architecture in this article, whose short, mid and long range lines are improved to make the interconnect resource has a better delay performance when the CLB tends to become larger and contains more programmable logic resource and the area of CLB grows larger, and compare its performance with the conventional FPGA’s routing architecture by modeling and simulation. Through the comparison, we know that using this new architecture, the double lines are average21.9%faster, the hex lines are average21.7%faster, and the lone lines are average4%faster. And this routing architecture has already been used in the FDP4P1FPGA chip, which is designed and taped out by ourselves. And we also have finished the performance test of its routing resources and proved the superiority of our idea.At last, we present a kind of scan chain who uses the DFFs in CLB as the scan DFFs for the test of interconnect resources. As this scan chain does not need additional DFFs, there are hardly any consumption on area, and this scan chain can improve the efficiency of interconnect recourse test. |
PDF Full Text Request