Research And Implementation Of FPGA Interconnect Structure Evaluation System

With the development of Field-Programmable Gate Arrays (FPGA), we have witnessed its widespread application, as well as increasing complexity in its architecture design. Considering that the programmable routing resource dominates the overall area overhead and signal delay of FPGA chip, the research on methodology of modeling and evaluation for FPGA interconnect architecture in this thesis has important theoretical and practical value.The methods of evaluating FPGA routing architecture in academic can be divided into two categories, assessing by CAD flow and predicting by analytical models, the former is more accurate but time-consuming, and the feature of the latter is just opposite. In terms of target architecture, most of current research are based on simple connection box/switch box model and just consider single-length wire segments, which are far from the interconnect structures of modern FPGA.In this work, we have proposed and implemented an interconnect architectural evaluation system to assess timing performance and area overhead for General Routing Matrix (GRM) based modern FPGA, and in which we have combined CAD flow with a statistical estimation model as a whole.The CAD flow consists of packing, placement and routing, and assesses routing structures by the delay of critical paths of test benches which are synthesized onto target FPGAs. Meanwhile, we have also proposed a novel architecture aware routing algorithm for the sake of structural evaluation, which not only can support GRM interconnect structure, but also can effectively improve the utilization of routing resource. The experiment result shows the utilization rate of hex lines and long lines has been raised by 6% and 8% respectively, for instance.In order to estimate interconnect architecture in a more essential way, we have also proposed an Average-Hops Statistical Model (AHSM), which can quickly give out a performance prediction based on architectural parameters such as segment type, channel width and drive relations. And the experiment shows that there is a good consistency between the indicator of AHSM and the actual timing performance measured by CAD flow. Then, we sum up an instructive formula as Hop2-3Area for comprehensively evaluating the timing performance and area, by employing AHSM to estimate hundreds of architecture designs, of which the selected representatives demonstrate to us that there is a trend of mixing multi-types of wire segments and importing bend lines in future interconnect architecture design.