Design And Test Methods About Communication Architecture Based On FPGA Of NoC

With the development of the microelectronics technology, the integrity of very large scale integrated circuit is getting higher and higher. SoC has to be designed with global clock synchronization, limited address space, unparallel communicate- on among multiple nodes and inflexible extension enough which has restricted in the scale and performance capabilities seriously in a single chip. NoC has been put forward the idea of the computer network technology to migrate to chip design. The IP cores communicate with each other by the wormholes exchange routing mechanism which has replaced the traditional bus architecture. NoC can solve the problems posed by the bus architecture. Besides, NoC has good expansibility, low transmission power consumption, low latency and parallel communication ability.This thesis is mainly targeted on verifying the effectiveness of the communication structure on the NoC. This have studied topology structure based on 2D-Mesh and the design and test methods about communication architecture based on FPGA of NoC. This thesis mainly includes three aspects: (1) the communication architecture to design on the NoC, the IP cores to add and the internal module to design. The internal module of NoC mainly include router, resource-network-inter- face and interconnects. (2) we have introduced the concept of FPGA, the design of software QuartusⅡdevelopment process and the NoC based on FPGA.(3) we use the related comprehensive software to test and verify the communication architecture and evaluate the performance of the NoC.In order to realize the practical application on the NoC, It have built a communication structure terrace of 2D-Mesh based on FPGA. We have accomplish- ed the data transferred and added in two ROM and saved the result into RAM by adding two IP cores. It have given the structural design, the verification process and the packet format defined about all modules on the NoC. Further more, This have given the area of the necessary comprehensive of all modules, power analysis, timing constraints and time-series analysis. It can verify the NoC architecture by downloading all to FPGA developing board.