| In digital signal processing (DSP) ICs and microprocessors, the datapath is the core where all computations are performed. A datapath compiler is generally used to automatically generate layouts for datapaths by taking advantage of the bit-sliced structure presented in datapaths. Conventional datapath compilers focus on using regularity to generate layouts with minimum area, while the timing issues are not well addressed. Some attempts are being made to attack this problem in synthesis tools, which employ logic optimization techniques to synthesize datapaths in a regularity-aware manner, and then generate netlists with placement data to guide the physical design. We approach this problem from the opposite direction, i.e., we start from physical design based on module generation and then plan to incorporate timing optimization techniques into the system in the future. The work presented in the thesis is the first step towards this direction.; A datapath compiler has been developed and implemented based on an object-oriented design that allows the future extension for static timing analysis and optimization. The timing issues have not been addressed directly in the thesis. A set of Java classes has been developed for design capture. A new type of over-cell routing algorithm designed specifically for datapaths has been proposed and implemented. This is the first time that a cell layout generation tool has been used to generate cells on the fly in a datapath compiler. Using CLASSIC-SC for cell generation is also the main reason that we can achieve technology portability. Other features of the datapath compiler include parameterization in bit width, the ability to deal with the irregularity that exists in real-world datapaths, and a GUI for capturing designs, displaying and exporting layouts.; A comparison with a custom layout shows that this new datapath compiler can produce comparable layouts in area while being technology portable. |
