Polymorphic network-on-chip datapath architecture for reconfigurable computing machines

Polymorphic processors have considerable advantages in performance over existing reconfigurable designs. Polymorphic processors combine the flexibility and ease of a general purpose processor with the performance optimizations made possible through reconfigurable arrays. Polymorphic processors provide all the ease of programming from a traditional general purpose processor while incorporating the significant performance gains that can be realized using reconfigurable arrays.;Polymorphic processors can be categorized by the level of integration between the general purpose processor and the reconfigurable array. At coarse levels of integration, the processor and reconfigurable array execute independently and exchange data utilizing bus structures. While these systems perform robustly for high level coarse grained data-driven optimizations, the overhead from data transfer limits the benefit to fine grained optimizations. Other approaches attempt a tighter coupling of reconfigurable arrays, using reconfigurable coprocessors and functional units, which allow good performance for fine grained optimizations, but find it difficult to perform well on coarse grained optimizations.;This thesis presents the new polymorphic NoC (PolyNoC) processor, which achieves an even more tightly coupled design than any prior work. The datapath of the processor is eliminated and replaced with a network-on-chip fabric. This fabric connects a system of reconfigurable arrays. These reconfigurable arrays are used to execute both standard instructions and new highly optimized application specific instructions. The PolyNoC processor is able to incorporate both fine and coarse grained optimizations, able to provide performance improvements for a wide range of target applications.;The PolyNoC processor creates unique design constraints resulting from the use of the NoC as a datapath. The impact of these constraints are studied and incorporated into the design of a NoC for the PolyNoC processor. A cycle-accurate simulator of the PolyNoC processor has been constructed and is used to examine the performance of the PolyNoC processor when executing unmodified, industry standard benchmark programs. To demonstrate the advantages of application specific extensions to the processor, accelerators are added for each benchmark. The performance of the PolyNoC processor is very promising.