Design And Implementation Of MIPS RISC Microprocessor Datapath

With the development of integrated circuit technology, SOC design becomes more and more popular. The SOC-based approach to embedded system design reduces the cost of development significantly, it also makes maintainance easier.The microprocessor is the core of embedded systems, it determines the performance of the entire embedded system. The MIPS instruction format is clear and compact; it can simplify the design of the microprocessor architecture, and achieves relatively good performance. The ultimate design is based on the MIPS instruction set, and it has five stages pipeline.Based on the research of MIPS instruction set, instructions and instruction addressing has been chosen to implement. The detailed analysis of execution, the functional unit designed includes: the memory unit of instruction and data, the register files providing high-speed operation, the arithmetic logical unit, the sign extend unit. We implement the data path of single cycle risk processor after all the modules are designed.As we know, the pipeline is the most important method to improve the performance of the embedded microprocessor. After completion of single cycle processor data path, we carefully analyze and design the pipeline processor data path and registers, and eventually realized the five stages pipeline processor data path.After the design is completed, we simulate all the modules, and download it into the FPGA development board. The final data path of the design supports 34 instructions in total, and reaches its highest frequency 40 M HZ.