| In DSP design, datapath restrains clock cycle and occupies significantchip area; therefore, it is the major factor of microprocessor performance aswell as the price. This text discusses the optimization of the rDSP data-pathdesign. The main content and innovation include:1. In analyzing the traditional logarithmic shifter implementation, the authorproposed a new scheme to implement interconnection, which uses2’scomplement code for shifter component directly, thus avoiding the impacton the critical path in the traditional design of the adder and reverse thecircuit.2. The author also completes design of a40-bit adder. By employing asquare carry-select structure, this adder calculates the carry-out of the16thbit from the carry chain, which enables it to support dual16-bit mode.Thereby, this scheme accelerates some DSP algorithms, and proposesoptimized algorithm for the carry chain within and/or between groups.3. The author analyses two kinds of traditional structures in realizing ALU.Aiming at the defect of splitting arithmetic and logical units, the authordesigned a new ALU architecture, which takes less consumption of area andexecution time.4. Multiplier is the key component of a DSP, in that the design of multipliercould determine the ultimate performance of the whole DSP. The Mac isimplemented by using improved Booth code,5-layered Wallace Treestructure and CLA adders, meanwhile focusing on the treatment of thesymbols of the signed multiplication. |
