| As we migrate toward ultra deep sub-micron feature sizes, integrated circuits are becoming increasingly complex, with very aggressive performance goals. In state-of-the-art integrated circuits, arithmetic datapath blocks are very commonly encountered. Some of the specific examples of arithmetic datapath blocks are multiplier, multiply-accumulator (MAC), sum-of-product, squarer, product-of-sum, shifter, non-standard sum-of-product, adder, subtractor, incrementor, decrementor, comparator, tree-of-adder or combinations thereof. These datapath blocks are used in applications like vector quantization, adaptive filtering, pattern recognition, image compression, decoding etc. Since datapath blocks perform computationally expensive operations, they tend to be found in the timing-critical path of the design. In addition, they consume significant amount of area in the chip, which aggravates the physical design timing closure problems as well. As a result, designing efficient datapath blocks is crucial to the continued success of future integrated circuit designs.;In the datapath design flow, specialized techniques need to be deployed in the Synthesis, Placement and Routing phases of the design process. This is important because datapath blocks pose different challenges (and optimization opportunities) at each of these three phases, which the general-purpose (random-logic oriented) design automation techniques cannot handle efficiently. In this research, we propose different techniques for datapath synthesis and datapath routing. Datapath placement is not included in the scope of this research.;We next mention the different techniques proposed in this thesis, for the arithmetic datapath synthesis. The key to the efficient performance of any synthesized arithmetic block is to design an appropriate architecture in the context of the surrounding circuitry and timing constraints. We propose different techniques to synthesize arithmetic Sum-of-Product (SOP) blocks. In one approach, we targeted timing-efficiency and in another approach, the aim was to reduce area. Next, several techniques are proposed to address synthesis of efficient 2-operand adders. We also discuss timing-driven techniques to design fast shifters and product-of-sum blocks. The final delay-efficient synthesis technique in this thesis discusses a block consisting of SOP, shifter and adder sub-blocks. In addition to the individual blocks, we also introduce a resource-sharing architecture, which can perform the operations performed by multiple mutually exclusive SOP blocks. After discussing the synthesis techniques, we propose specialized dedicated routing methodology for datapath designs.;The techniques presented in this work are quite general and do not depend on specific technology domain or the library. To prove this, results are validated using different types of designs, technology libraries and timing constraints. |
