Design Of Resilient Packet Ring MAC Datapath In MSTP

With the development of network technology, widespread used and service growth in demand, it is necessary to transport IP data on telecommunication network, thus Next Generation Network came out. NGN is an integeration open network architecture, which is based on packet. It can provide services, including voice and video, data and multi-media. Multi-Service Transport Platfor which based on Resilient Packet Ring has attract much attention in construction of information port, has to be used in construction of MAN.RPR proposed by IEEE which to be used for optimization of data transport on ring topology, is a new Media Access Control protocol. It is driven by market demand, thus it attracts great attention as soon as being proposed. Immediately, serval working groups have been established by International Organization for Standard to work for standardization of RPR, and the interoperability of equipments provided by different manufacturers is an important agenda.Basic data unit of RPR data frame.RPR ring is composed of two ringlet, one is clockwise ringlet which to be called outer ringlet , and another is inverse clockwise ringlet which to be called inner ringlet. Two ringlets provide RPR with more robustness, protection with two ringlets is called Resilient, RPR offers different modes of distribution of bandwidth for each service type, in order to meet the quality needs of service requirements.The fairness algorithm prevent each node from bandwidth congestion, and provide the maximum bandwidth. RPR can seamless integrated with MPLS, to provide utilization of network and traffic performance for multi-service switch, at the same time, to improve efficiency of network and stability of Traffic EngineeringAccording to standard IEEE 802.17, determine the design scheme of this article through analysis of RPR key technology, such as RPR frame format,ring topology,network performance,protection and recovery of network fault.This paper presents a new design scheme of RPR MAC datapath, which has three submodules, including data access,data receiver and filter,data transmit. Receive operation provides the following functionality, receive of frames, accouting, and direction to appropriate locations, detection and monitoring of frames arriving on the wrong ringlet. Transmit operation provides the following functionality, ringlet selection, frame field initialization, stage queue selection, add traffic statistics, transmit selection and transmit traffic statistics. Link rate synchronization and traffic fairness control have to be considered in the design. Queue, Bus and parallel CRC,which are important to RPR, also being discussed in detail.This system complete the design with synthesizable subset of Verilog HDL, and C/C++ to be used for modeling, SystemVeilog to be used in verification. Design and implementation of this system is based on ISE (Integrated Software Environment) of Xilinx.Finally FPGA physical verification is completed on Xilinx Corp Spartan3E XC3S500E device.