Reduced order modeling and analysis for VLSI RLC interconnect

In very deep sub-micron (VDSM) IC design, interconnect become the dominant factor of system performance. Accurate yet fast timing analysis is crucial to maintaining performance and reducing time-to-market. Due to the special features of on-chip interconnect circuits (large amount and size, stiffness etc.), it is time consuming to use conventional simulators such as SPICE as built-in interconnect analysis engines. Model order reduction is the key to speedup timing analysis and verification. Meanwhile, with the advent of System-On-Chip (SoC) and as switching frequency increasing, inductive effects need to be considered while inductance aware interconnect modeling and analysis becomes much more challenging.; In the first part of the dissertation, we explore the frequency domain model order reduction for RLC interconnect using amplitude and phase response approximation. (1) We propose the concept of AP moments, which has strong physical meaning and more general than central moments for RLC interconnect analysis. Closed-form formulas are derived for calculating AP moments directly from circuit response moments. Based on explicit AP moment matching, efficient delay models can be constructed for RLC interconnect delay estimation. (2) To verify detail waveform, segmented Chebyshev polynomial expansion method is proposed for wide-spectrum frequency response approximation with near optimal results. The headache problems existing in poleextraction based reduction approaches can be avoided. Also, built-in frequency domain error-control makes this approach more practical.; In the second part, we study delay estimation methods for gate-level timing analysis and optimization. (1) We propose an efficient hierarchical and incremental reduction technique for RLC tree delay estimation. To preserve stability, we propose a novel method by employing realizable reduction and using lower order Hurwitz polynomials. There is no need to compute moments during the reduction while they can still be matched implicitly. (2) We study the gate delay estimation with the presence of RC/RLC load. For deep-submicron applications, we propose a new effective capacitance computation method by using a modified output current model and a new definition of effective capacitance. Comparing with the original approach, the new method achieves significant accuracy improvement.