| Recent interest in wave-particle interactions in the Earth's Van Allen belts has spurred the construction of a new generation of plasma wave receivers, scientific instruments that measure electromagnetic signals while aboard a satellite flying through the upper atmosphere. Such receivers have stringent analog-to-digital conversion requirements, as they must simultaneously capture multiple signals spread over a broad frequency range (from 100 Hz to 1 MHz) and spanning a wide dynamic range (90 dB) while consuming minimal power. In addition, they must maintain this performance as they fly through the damaging radiation environment of the Earth's radiation belts.This dissertation describes the specification, design, implementation, and testing of the SVADC-1, a radiation-hard, 12-bit, pipeline analog-to-digital converter that meets these requirements. A consideration of the spectrographic nature of plasma wave analysis, coupled with the common occurrence of simultaneous strong and weak phenomena, identifies the spurious-free dynamic range (SFDR) as a key metric for plasma wave receivers. A subsequent investigation of quantization shows that, to achieve the 90-dB SFDR required (assuming 100-Hz/bin spectral resolution), a conversion of just 12 bits is sufficient. In implementing such conversions, though, traditional pipeline converters suffer from quantization nonuniformities that reduce their SFDR. These nonuniformities are primarily due to the mismatch between the analog stages of the pipeline and the corresponding digital reconstruction. Hence this dissertation introduces a novel self-calibration technique based on DAC differencing that corrects for this mismatch in the more malleable digital domain. As a result, after self-calibration the SVADC-1 achieves a wideband peak SFDR of >90.9 dB while sampling at 5 MS/s and consuming just 48.8 mW.In addition, the SVADC-1 is radiation-hard. Traditionally, radiation tolerant electronics rely upon specialized manufacturing processes to guarantee radiation hardness. However, these specialty processes are often expensive and hard to obtain. In contrast, the SVADC-1 is fabricated in a commercial, 0.25-mum CMOS manufacturing process, and employs radiation-hardness by design---including techniques such as enclosed terminal layouts for selected transistors, self-resetting architectures, selective analog overdesign, and the use of guard rings---to compensate for radiation-induced degradation and upsets. In total-dose radiation testing of the SVADC-1 by 50-MeV protons, it maintains a performance of >90.1-dB peak SFDR while sampling at 5 MS/s and consuming &le60.2 mW up to a total dose of 1 Mrad(Si), experiencing a slight decrease to &ge88.2-dB peak SFDR and &le60.5 mW up to 2 Mrad(Si) (the highest dose tested). And in single-event radiation testing of the SVADC-1 by 25-MeV/nucleon heavy ions, it displays no latchup through an LET of 63 MeV-cm2/mg (the highest tested LET) at elevated supply (2.7 V) and temperature (131°C). |
