Font Size: a A A

Research On High Resolution Acquisition Technology Of Wideband Signal Based On Array Sampling

Posted on:2021-01-23Degree:DoctorType:Dissertation
Country:ChinaCandidate:J GaoFull Text:PDF
GTID:1368330611477331Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
Acquisition system with high-speed and high-resolution technology plays a core role in the defense fields such as modern precision guidance,aerial remote sensing,and space laser detection.With the increasing complexity of signals in the system,higher requirements are imposed on the instantaneous bandwidth and recognition accuracy of the acquisition system.However,due to the limitations of the existing integrated circuit technology,the analog-to-digital converter(ADC)chip which supports the high-speed acquisition system has always failed to meet the ultra-high-speed broadband signal capture requirements in terms of sampling rate and resolution.In order to break through the limitation of the performance of a single ADC chip,the parallel-based sampling technology has become an effective method to improve the sampling rate or resolution of acquisition system.Based on the above background,this dissertation focuses on the goal of high-speed and high-precision digital acquisition technology,and studies a technical approach to achieve high-speed and high-precision acquisition through a hybrid parallel architecture.As the number of parallel paths increases,errors such as offset,gain,and time mismatch in the system severely reduce the system's signal-to-noise ratio.In order to eliminate the influence of mismatch errors on the system,this dissertation studies the characteristics and behavior models of channel mismatch errors in hybrid architectures,and proposes two error estimation and correction methods.Specifically,the research is mainly carried out from the following aspects:(1)Statistical analysis theory is used to mathematically model the quantization process in ADC sampling,and a quantization model of parallel sampling method is proposed.With the help of statistical analysis tools,the quantization process of any sampling system is modeled as a pulse sequence that samples the input probability density function,and the relationship between the number of quantization bits and the sequence density is established.Based on this model,a quantization model of parallel sampling method is proposed,and the quantization bit improving process of parallel sampling is studied.(2)Two kinds of high-resolution sampling technology based on parallel sampling are researched.Because the traditional time synchronized ADC(TSADC)structure is insufficient under some condition,a quantization interleaved ADC(QIADC)sampling structure is proposed.The traditional TSADC method was quantitatively analyzed.Based on the theoretical derivation,the expressions of the quantization resolution and effective resolution enhancement effect of the method are given,and the applicable conditions of the method are creatively pointed out.Aiming at the shortcomings of traditional methods,an improved QIADC structure is proposed.This structure interleaves the quantization unit in the vertical direction,which doubles the ADC's quantization ability and eliminates the dependence on the system noise level.In addition,the core QIADC quantization theorem is given,and the resolution improvement process of the method is theoretically proved by a parallel sampling quantization model.(3)Combining the different characteristics of two one-dimensional parallel alternate sampling structures,a two-dimensional array sampling structure is proposed.This technology improves the traditional one-dimensional interleaving sampling design method.It uses QIADC design in the vertical direction and time interleaved ADC(TIADC)design in the horizontal direction.It constructs a two-dimensional hybrid sampling architecture,effectively breaking the limits of single-chip ADC sampling rate and resolution indicators.A checkerboard model of ADC deployment is proposed,and different configuration schemes are designed in the same sampling array through the dynamic reconstruction of hardware modules.The sampling system based on the hybrid architecture can realize the real-time conversion of sampling rate and resolution resources in a set of hardware structures,and solves the problem that it is difficult to balance the sampling rate and resolution.(4)This dissertation analyzes the characteristics of multi-channel mismatch errors in hybrid architectures and the impact of errors on system performance,and proposes two error correction methods in a targeted manner.In order to eliminate the static time mismatch error between the channels of the system,an error estimation and correction method based on first-order statistics is proposed,and an improved least mean square(LMS)algorithm is used to adaptively correct the time error.The system's spurious free dynamic range(SFDR)before and after applying the algorithm is increased by about 9 dB,and the convergence speed is better than similar algorithms.Aiming at the characteristics of wideband signals,a frequency response non-uniformity error correction algorithm based on a compensation filter is proposed to eliminate the impact of frequency response mismatch errors on the system.Experimental results show that for 2GHz high-frequency signals,the system SFDR is improved by 23.8dB,and for wideband multitone signals,the algorithm also has a good correction effect.(5)A digital post-processing technique based on a cascade filter is proposed.Aiming at the problem of how to further improve the system effective number of bit(ENOB)after the design level of the hardware circuit reaches the limit,this dissertation analyzes the noise source and noise characteristics of the system,and studies a variety of digital postprocessing noise reduction techniques.In order to overcome the shortcomings of high sidelobe ripple and transition bandwidth of filters in traditional noise reduction methods,an improved method based on cascaded filters with low computational complexity and good stability is proposed,which is of great significance for improving the accuracy of the system.(6)Design and implement a high-resolution digital three-dimensional oscilloscope principle prototype.Based on the overall design of the system,an acquisition system with a maximum resolution of 12 bits and a maximum sampling rate of 20 GSPS was established to provide an experimental platform for the verification of key technologies.In terms of hardware design,a scheme for switching between common sampling and high-resolution sampling modes by dynamically configuring the sampling clock chip and ADC is proposed.In addition,the problem of data synchronization between multiple ADCs in the system and during storage is studied,and a multi-channel data synchronization calibration scheme is proposed to solve the problem of synchronization of large parallel data.The digital three-dimensional oscilloscope principle prototype is a concentrated reflection of high-speed and high-precision digital acquisition technology.The system pioneered the use of arrayed acquisition to achieve double improvement in sampling rate resolution.It has been verified that the system's comprehensive technical indicators are in the leading position in China.
Keywords/Search Tags:Analog-to-digital converter(ADC), high-speed and high-precision sampling, quantization bit, effective number of bit (ENOB), array sampling, nonuniform frequency response error, reconfigurable hardware, digital threedimensional oscilloscope(DPO)
PDF Full Text Request
Related items