Lateral superjunction power MOSFETs

Power semiconductor devices play a crucial role in the efficient control of power used in electronic systems. There is a great need for the reduction of the power losses during switching and on-state conduction of such devices.; In this thesis a novel lateral power MOSFET compatible with CMOS on SOI technology and using the superjunction concept is proposed.; The superjunction (SJ) concept, requires the use of a drain drift region consisting of alternate n- and p-type, highly doped regions. These regions are fully depleted in the current blocking mode of operation to ensure a high breakdown voltage. The implementation of the SJ concept in lateral power MOSFETs in silicon-on-insulator (SOI) technology combines the reduction in onstate power losses with complete suppression of substrate currents and latchup, easy integration of a wide range of power and small signal analog and dense CMOS active devices on the same chip, increased packing densities, fast switching speed and low leakage currents.; A method of fabrication of the device is proposed, using selective area growth (SAG) to implement the SJ structure in the drift region of the SOI LDMOS transistor. Process and device simulations are carried out. The novel SJ Power LDMOST exhibits a specific on-resistance of 1.65mOcm 2 for a 150V class and breaks the silicon limit. By comparison to conventional LDMOST SOI devices, the proposed structure offers an improvement of over 60% in specific on-resistance and in the gate charge on-resistance figure of merit (Qg.Ron = 0.23O.nC) thus reducing power losses during device switching and on-state conduction.