REBULF Theory And New Technology For Lateral Superjunction Power Devices

Modern power electronics technology requires power devices with superior performance in high voltage, high speed and low loss, super junction (SJ) device as a new type of power device can further improve the breakdown voltage (BV), reduce the specific on-resistance (Ron). For the SJ-MOSFET, the constraint relation between Ron and BV is improved form 2.5th power to 1.3th power, which breaks the"Silicon Limit"in conventional device, and improves the tradeoff between the BV and Ron. As SJ technology is applied in LDMOS (Lateral Double-diffused MOSFET), LDMOS, the key device in power integrated circuit, becomes SJ-LDMOS to improve the performance of device. However, the vertical electric field destroys the charge balance of SJ resulting in the low BV in the lateral SJ devices, which is called"substrate-assisted depletion effect". This effect reduces the performance of SJ-LDMOS, and embarrasses the development of lateral super junction power device.In this dissertation, REBULF (Reduced Bulk Field) technology for the lateral SJ device is proposed by analyzing the breakdown characteristic of device. Optimizing bulk field can promote the charge balance of SJ, and reducing the electric field in bulk silicon can increase the vertical BV. According to the REBULF technology, an SJ-LDMOS based on charge compensation is investigated and implemented experimentally, and two new structures are presented basing on enhanced dielectric electric field and adjustable potential, which improves the BV of lateral SJ device. The detail contributions of the dissertation are listed as followings:1. REBULF model for lateral SJ power device is proposed to improve the BV by optimizing bulk field. The field is optimized by these three methods: compensating charges, enhancing dielectric electric field, and adjusting potential. First, added compensation charges in drift region take on the vertical depletion, which ensures the charge balance in SJ and optimizes the bulk field. Second, the electric field in dielectric layer is enhanced by high density interface charges, which reduces the vertical electric field in SJ, improves the charge balance of SJ, and increases the vertical BV of device. Third, the vertical potential is adjusted by utilizing specific back-gate character of SOI device, which optimizes the bulk field distribution and promotes the charge balance.2. Basing on charge compensation REBULF model, the surface low on-resistance path (SLOP) LDMOS is researched and implemented experimentally. A heavily doped SJ region provides a low on-resistance path in this device, and then thick N-well or N-epi layer sustains vertical voltage, which reduces the affect of vertical field on lateral SJ and improves the charge balance resulting in increased BV. In addition, SLOP LDMOS can be applied in power IC for compatible BCD process because the SJ is shallow on the surface of device. A 500 V class SLOP LDMOS is implemented in a BCD process. The experiment result shows a power figure of merit (FOM, FOM = BV2/Ron,sp) of 2.6 MW/cm2 , when pillar width is 3μm.3. Basing on enhanced dielectric electric field REBULF model, two kinds of SJ-LDMOS with enhanced electric field in BOX are proposed, which are with added fixed charges at surface of BOX and with dynamic buffer layer. Enhancing electric field in the BOX by interface charges reduces the vertical electric field in SJ, which eliminates the affect of the vertical electric field on the SJ charge balance, while the ability of the device vertical BV is increased. Dynamic buffer layer has the ability to adaptively enhance electric field. According to the characteristic of charges accumulation in the trenches, charges can be accumulated with the longitudinal electric field magnitude and distributed according to need, to achieve the perfect results. Simulation results show that the BV of the SJ device is to 220V, and the average lateral field is to 22V/μm, while the length of the drift region is 10μm.4. Basing on adjustable potential REBULF model, SOI SJ-LDMOS with dynamic back-gate voltage is proposed. Utilizing specific back-gate character of SOI device, the vertical electric field distribution in SOI SJ-LDMOS is optimized by dynamic back-gate voltage. Electrons and holes are attracted the bottom of the BOX to improve the charge balance. Due to partial vertical voltage transferred to source region from drain region, this increases the vertical BV.In addition, a new PSOI SJ-LDMOS with charge compensation has been studied in this dissertation. It reduces the specific on-resistance by low on-resistance path at the top of device with heavily doped SJ region. After etching buried oxide at the drain region to add an N-buffer region, the PN junction in substrate sustains more vertical voltage. It compensates the charges in SJ, increases the vertical BV, while preserves the isolation advantage of SOI device.