New Lateral Superjunction Power MOSFETs Based On Electric Field Modulation

With the rapid development of very large scale integration(VLSI) technology and power electronic device technology, power integrated circuit(PIC) and high voltage power integrated circuit(HVIC) are being widely used in many fields. Based on a great variety of characteristics such as planar technology, easy integration, high voltage, low power consumption and high frequency, Lateral Double Diffused MOSFET(LDMOS) becomes the core of the PIC. Super junction(SJ) device has a very low resistance under a certain voltage, which can breakdown the limit relationship between the specific on resistance(Ron,sp) and the breakdown voltage(BV). The SJ applied to the LDMOS forming the SJ-LDMOS that can greatly reduce the conduction loss and becomes the research hotspot of power devices. However, in the process of the SJ-LDMOS implementation, due to the substrate assisted depletion(SAD) effect, the electric charge is not balanced, and the overall performance of the device is decreased. Consequently, the SAD effect limits the SJ-LDMOS application in power integrated circuits.Three new SJ-LDMOS structures are proposed and analyzed in this paper. On the basis of the traditional Buffer SJ-LDMOS devices to eliminate the SAD effect, the BSD SJ-LDMOS, SIPOS SJ-LDMOS and SOSJ-LDMOS have been proposed to further optimize the performance of the SJ-LDMOS, and have also been verified by ISE simulations. The electric field distribution on the surface of the SJ-LDMOS is optimized by the means of electric field modulation, which improves the performance of the devices. The detail contributions of the dissertation are listed as followings:1. New super junction with different doping of the buffered layer(BSD SJ-LDMOS) is proposed based on the traditional N-Buffer SJ-LDMOS. A detailed analysis of the BV and electric field distributions is discussed when the device is in the OFF state, by means of simulation software. A new electric peak generated by the different doping of the buffered layer is introduced into the electric field on the surface of the drift, which optimizes the electric field distribution on the surface and improves the BV of the device. Meanwell, the impact of the number of partitions on the overall performance of the BSD SJ-LDMOS is also discussed. When the number of partitions is three, the surface electric field of the device has achieved the optimal distribution and the BV the device has reached saturation. The BV of the BSD SJ-LDMOS has been increased by 32% compared with N-Buffered SJ-LDMOS in the same drift length and the lateral BV unit reaches 18.48 V/?m. The BSD SJ-LDMOS with the BV of 382 V and Ron,sp of 25.6 m?·cm2 breaking the limits of the LDMOS with BV of 254 V and the Ron,sp of 71.8 m?·cm2. Finally, the process of the BSD SJ-LDMOS is well introduced.2. New super junction with a semi-insulation poly silicon layer(SIPOS SJ-LDMOS) has been proposed based on the traditional N-Buffer SJ-LDMOS. In order to take full advantage of SJ structure, the SIPOS layer is applied to the SJ-LDMOS to achieve the effect of the complete 3D-RESURF(Three-dimensional Reduced Surface Field) for the SJ-LDMOS. The surface electric field is modulated and becomes more uniform by the electric field modulation effect due to the SIPOS layer. The BV and electric distribution of the SIPOS SJ-LDMOS is well analyzed using simulation software. The main physical model is introduced for simulation, at the same time. In addition, the problems of the leakage Current of SIPOS SJ-LDMOS in the OFF state have been analyzed. In the virtue of the ISE simulation, the BV of the SIPOS SJ-LDMOS has been increased by about 32% compared with the N-Buffered SJ-LDMOS and the Ron,sp is decreased by 33%.3. A novel SOSJ-LDMOS(Step-Oxide Super Junction LDMOS) structure is proposed and optimized which allows the high BV and low Ron,sp. The proposed structure overcomes the effect of thick field oxide formed by shallow trench isolation(STI) process in conventional N-Buffered SJ-LDMOS, effectively enhancing the performance of the SJ-LDMOS. Thanks to the step oxide layer, a new electric field peak has been introduced in the surface electric field distribution, which makes the lateral surface electric field more uniform in the OFF state. And due to the thinner oxide layer, in the ON state the majority of electron current is accumulated near the top surface under the field plate and the thinner oxide layer also provides a wider current flowing path. In the virtue of ISE simulation, not only has the BV of SOSJ-LDMOS been increased but also the Ron,sp has been reduced simultaneously compared with the N-Buffered SJ-LDMOS in the same drift length. In addition, when SOSJ-LDMOS and N-Buffered LDMOS are at the same BV, the Ron,sp of SOSJ-LDMOS is decreased by 26.3~38.9%, compared with the N-buffer SJ-LDMOS.